I need help with verilog code, I am in trouble


I am basically setting different control signals for the ALU to perform operations in verilog. But I have tried all possible ways of writing what I want but in vain, can you help me out. How should I set these control signals at particular 3 bit alu states;

This is my code, i have all possible assignments;
(sorry, its inverteed and i don't know how to rotate it because the website i upload pictures on automatically rotated it this way)

Initial declarations;

input [1:0] op, src, srl, dst_ram_mux, dst_q_mux;
input inv_s, inv_r, sel, dst_ram_en, dst_qen, dst_y, cin, reg_wr, cp;

 95 always @(i[5] or i[4] or i[3])
 96 begin
 97 if( i[5]==0  && i[4] == 0 && i[3] == 0)         // this is add   S+R
 98 begin
 99      cin <= 0;
 100     assign sel = 0;
 101     inv_s <= 0;
 102     assign inv_r = i[5] & i[4] & i[3];
 103     op[1] = i[5] & i[4] & i[3];                                        
 104     op[0] = 0;
 105 end

The 'end' for the always is way below at line 327, not seen here

The errors for all assignments;

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Best Answer

Read the error message:

A net is not a legal lvalue in this context

  • Procedural blocks can only assign registers types (Verilog:reg,SystemVerilog:logic/bit/reg). The assignment cannot be done to a input either
  • Combinational logic should have blocking assignments (=) only, not non-blocking (<=)
  • You should not used procedural continuous assignments (assign inside a procedural block)
  • Every assigned bit must have an assignment for each condition. Otherwise a latch is inferred. An easy strategy is to assign default values to all registers at the top of a procedural block, the remaining code overrides the default.

Other Guidelines:

  • Bit expatiation is not necessary:
  • i[5]==1 && i[4]==0 && i[3]==1 --> i[5:3]==3'b101
  • Use auto sensitivity list for combination always @* (or SystemVerilog's always_comb)
  • Long nested else-if comparing the same values bits can use a case statements

always_comb begin
  /* default assignments: e.g: cin='1; op='0; */
    3'b000 : begin /*S+R code*/ end
    3'b001 : begin /*S-R code*/ end
    3'b010 : begin /*R-S code*/ end
    // ... Other conditions ...
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