Identification of hardware interrupts in microprocessor 8085

I didn't read you document really, but I can understand why you are confused. But it is a very simple concept really. Let me explain.

Triggering: This means making a circuit active. Making a circuit active means allowing the circuit to take input and give output. Like for example supposed we have a flip-flop. When the circuit is not triggered, even if you give some input data, it will not change the data stored inside the flip-flop nor will it change the output Q or Q'. Now there are basically two types of triggering. The triggering is given in form of a clock pulse or gating signal. Depending upon the type of triggering mechanism used, the circuit will become active at specific states of the clock pulse.

1. Level Triggering: In level triggering the circuit will become active when the gating or clock pulse is on a particular level. This level is decided by the designer. We can have a negative level triggering in which the circuit is active when the clock signal is low or a positive level triggering in which the circuit is active when the clock signal is high.

2. Edge Triggering: In edge triggering the circuit becomes active at negative or positive edge of the clock signal. For example if the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes from low to high. Similarly input is taken at exactly the time in which the clock signal goes from high to low in negative edge triggering. But keep in mind after the the input, it can be processed in all the time till the next input is taken.

That is the general description of the triggering mechanisms and those also apply to the 8085 interrupts.

The 8085 has different instructions for accessing main memory and I/O 'memory'. In addition to the standard memory interface pins the 8085 also provides a pin that identifies whether a memory access cycle is accessing main or I/O. This extra line is used in the select logic of both main and I/O 'memory'.

But there is no law that I/O can only be accessed by I/O instructions: in a small system the highest address line could be used to distinguish between memory (a15=0) and I/O (a15=1), so we get 32Kb for real memory (ROM and RAM) and 32 Kb for I/O.

Note that it is even possible to use the I/O addresses to access RAM, but that is less useful because there are only 256 I/O addresses and the addressing modes available for these addresses are very limited.