jfet
When a reverse bias voltage is applied between the gate and the source, depletion layer is formed between the p-type and n-type materials in the JFET. My question is why isn't it symmetrical? Why does it move more towards the drain than towards the source?
Also, my text book tells that this happens because there is more voltage drop near the drain than near the source. Please explain this statement also.
It's the direction of the arrow that tells you:
N-Channel
P-Channel
The arrow points from P to N (like a diode) so you can tell which is which channel wise. For example in the top diagram, the arrow points to the channel, so the channel is N-type. In the bottom diagram it points away, so the channel is P-type (i.e. from P to N)
To clarify, this also applies to the symbol that has the gate connection drawn in the middle:
As far as I am aware, this should be used only when the source/drain are interchangeable, but is often used in error (many JFETs are not symmetrical so cannot be used either way round)
If a JFET is symmetrical, it can be used either way round and work just the same. In this case I think it is just convention to call one terminal source and the other drain even though it doesn't matter in practice.
However, some JFETs are designed so the channel is not the same thickness all the way along, and gate-drain capacitance differs from gate-source capacitance. This will matter little for many applications and the device can still be used either way round, but may be important in some (e.g. high frequency) applications.
I couldn't find any good references that go into detail on the subject quickly but Google for "Asymmetrical JFET" and have a read of the various patents. Also "Art of electronics" has a brief mention of this.
Its because you did not check your device specs . Its a n-ch JFET that needs negative Vgs or use a p-ch with +Vgs.
You need to linearize the Jfet with negative feedback on the drain to gate.
Choose the feedback R ratios wisely to bias the Vgs for desired VGA response. If you want + bias then use pch JET
So include 100k D to G and series R from Vctrl to Gate to check for linearity over input control range Idss at Vgs=0 and Vth = 4V
If the inverting input is not = +Vcc/2 then it wont work well. If Vds is not sufficiently biased, it wont work well.
The Vcc/2 bias screws up the Vgs bias when feedback for JFET so start with basics with no Op Amp
Best Answer
Take a look at this: -
Because the drain is more positively biased than the source, the depletion around the drain end of the device has to be "more" for any given gate voltage. More reverse bias equals bigger depletion layer. Clearly the picture isn't perfect because there will still be a depletion layer between gate and source but hopefully you get the general idea.
This is probably a more accurate picture: -