In CMOS, can I assume the delay of a multiplexer is negligible compared to the delay of an inverter

asiccmosdelayinvertermultiplexer

Let say I have a ring oscillator, and I modify the ring so that the output of an inverter is connected to an input of a 2-to-1 MUX, and the output of the MUX is connected to the input of the next inverter (see picture: http://imgur.com/i0Fafls ). Assuming I have an odd number of inverters, this structure allows me to skip some even number of inverters and still have an oscillating output. For example, let say I have 9 inverters and I decide to skip the first 4 inverters. The remaining 5 inverters forms a regular ring oscillator. My question is: Would the frequency of the output produced by this 5-inverter ring oscillator be significantly differently from the case where the same 5 inverters are connected directly without any MUX between adjacent inverters?

In other words, in CMOS, can I assume the delay of a multiplexer is negligible compared to the delay of an inverter?

Best Answer

You cannot really make any such assumptions in general.

If you want to know how the delays for a certain kind of multiplexer/inverter combination relate to each other, you have to check their data sheets. What I would expect to find there is that a single inverter is one the simplest kinds of gates, so it probably has the lowest delay - when comparing devices made with the same technology. However, the difference between devices made with different technologies can be so large that normally the choice of technology is probably the largest decisive factor for the delay. For example: at 25C & 5V, a 74HC04 has a typical propagation delay of 7ns, and a 74HC157 has 11-12ns. Decreasing the voltage would increase the delay. By changing to 74LVC technology and decreasing the power supply to 3.3V, you can get a 74LVC04 with a typical delay of 2ns, or a 74LVC157A with a delay of 2.5-2.7ns.

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