Loop synthesis vhdl

processsynthesisvhdl

Suppose we have an iterative algorithm like:

r(j) := f(r(j-1))
r(0) := value

And that vhdl i implemened a process for such algorithms (assuming a bit of pseudocode…)

process(x) is
  variable r := x;
  variable k := 0;
begin
  while(k < MAX) loop
    r := f(r); -- f( ) could be a vhdl function
    k := k + 1;
  end loop;
  y <= r; -- y is the output of the entity that embodies this process
end process;

Would the synthesis result in a cascade of f logic without pipelining?

Update…

I think i could write something equivalent with a for ... generate
would that make some difference in synthesis terms?

Best Answer

Your code cannot be synthesised by the logic synthesizers I know. While loops and for loops are unrolled by the synthesizer and must thus have constant bounds. If you want the result to be combinatorial, use a for loop instead:

process(x)
  variable r: <r-type> := x;
begin
  for k in 0 to MAX - 1 loop
    r := f(r);
  end loop;
  y <= r; -- y is the output of the entity that embodies this process
end process;

Note that you can indeed do the same with a generate statement, the synthesis result would be exactly the same:

type r_array is array(0 to MAX) of <r-type>;
...
g: for k in 1 to MAX generate
  r(k) <= f(r(k - 1));
end generate g;
r(0) <= x;
y    <= r(MAX);

If you want a sequential result, processing one iteration per clock cycle, use something like:

process(clock)
  variable r: <r-type>;
  variable k: natural range 0 to MAX;
begin
  if rising_edge(clock) then
    if reset = '1' then
      k    := MAX;
      done <= '0';
    else
      if start = '1' then
        r    := x;
        k    := 0;
        done <= '0';
      end if;
      if k = MAX then
        done <= '1';
        y    <= r; -- y is the output of the entity that embodies this process
      else
        r := f(r);
        k := k + 1;
      end if;
    end if;
  end if;
end process;
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