gccmsp430watchdog
I'm using GNU v4.9.1 compiler, and I'm just trying to work with WDT timer:
void __attribute__((interrupt(WDT_VECTOR))) WDT_ISR(void)
{
P2OUT ^= BIT1;
}
When trying to build it, I keep getting these errors:
section __interrupt_vector_11' will not fit in region `VECT11'
region `VECT11' overflowed by 2 bytes
Do you have any idea, what could cause this?
Thanks.
Most micros support a low-power 32.768 kHz watch crystal oscillator with some kind of prescaler and timer interrupt. Set the prescaler so the timer is counting slowly and the interrupt happens at the period you desire.
Some micros also have a built-in low-power RC timer if exact timing isn't critical.
The datasheet for any low-power micro will list the power with 32.768 oscillator (and nothing else) running. It's pretty close to zero. You can do the math to see if this is acceptable, and compare it to the current drawn by the watchdog.
OK, for example on the msp430f2013, let's look at power in the datasheet.
0.5 μA is almost zero, although it is five times the true OFF mode.
For more detail, we can look inside the datasheet.
Going from LPM4 (everything off) to LPM3 (running the oscillator) is the difference between 0.5 μA and 1 μA.
Suppose the battery is CR2032 with 225 mAh capacity. Then standby in LPM4 is about 50 years and in LPM3 is about 25 years. 25 years is long enough for many applications, because the ON-current (during the measurement itself) dominates the consumption.
The MSP430G2452 has three Timer A bugs in both revisions, any of which might be affecting you. They can be read in the Errata for the chip. I believe maybe Bug TA12:
Interrupt is lost (slow ACLK):
Timer_A counter is running with slow clock (external TACLK or ACLK)compared to MCLK. The compare mode is selected for the capture/compare channel and the CCRx register is incremented by one with the occurring compare interrupt (if TAR = CCRx). Due to the fast MCLK the CCRx register increment (CCRx = CCRx+1) happens before the Timer_A counter has incremented again. Therefore the next compare interrupt should happen at once with the next Timer_A counter increment (if TAR = CCRx + 1). This interrupt gets lost.Workaround: Switch capture/compare mode to capture mode before the CCRx register increment. Switch back to compare mode afterwards.
Even if this is not the case, you can easily fix this. You are using the default 1MHz Master clock. You can change this to 2 MHz or 4 MHz with a simple code change, at which point the same divider would produce a VLO of 24KHz or 48Khz. This would allow you to set a timer count a bit higher, again either 12 or 24, avoiding the lower count issue. Of course, testing is needed to be sure.
Your alternative plan also works. If you are not too concerned with low power, simple delays would work. Of course, as this is running on the Master clock of 1Mhz instead, you will need to calculate an apropos delay, and realize that there will be some slight drift.
Best Answer
I'm taking a wild guess here, but maybe you've accidentally enabled Large Memory Model (on newer MSP430s it allows you to address up to 1MB of memory), which turns function pointers to 32-bit, so the pointer to your WDT_ISR() overflows the interrupt vector by two bytes. Check if you're passing the correct compiler flags to GCC.