I have a pic32 and I'm talking to a spi nor part to store some data. Now for burst write my flash supports 256 bytes at a time and I want to use my DMA to transfer this. However the part requires that CS stay low for all 256 bytes. I was reading both datasheets and trying to understand CS behavior but I don't quite understand.
I took a look at what happens when I read a status register from the flash which requires me to use DMA to write 4 bytes. On the analyzer I see that CS stays low for the whole transfer which is what I want. But how does it know? There's only one register to write for the spi buffer (not using fifos / enhanced mode). So how the heck does the hardware know I'm not done after the first byte?
My only thought is that there is a buffer you write to, and another buffer that shifts out bits. So if I fill the write buffer before the shift buffer is empty maybe that keeps CS low. I can't prove it though and I'd like to understand how it works before I just blindly use it.
Best Answer
The behavior you observe is due to SPIxCON.MSSEN bit being set ( it is cleared by default so apparently it was you who set it blindly before understanding how it works - sorry, couldn't resist ). In this mode SS stays asserted as long as there is data to be transmitted, and it will stay low if you happen to write to the buffer during transmission. This as well as other useful and fascinating things can be learned by studying Section 23 of PIC32 Family Reference Manual, a link to which is conveniently provided on any PIC32 micro product page at Microchip web site.
You don't have to do this though. Just leave this bit in its default state and drive SS manually.