Port full register file from/to a verilog modue

verilog

How can I port out/in a register file with Verilog (synthesis-able code). At this specific code a generate loop code is not viable due to the architecture of an existing code.

A test code, trying to port to/from my module a dynamic register file, with size based on a parameter.

module mux_test (/*AUTOARG*/
   // Outputs
   ro,
   // Inputs
   clk, rst_n, ain, v, din, bias
   ) ;
   parameter D_WIDTH=8;
   parameter A_WIDTH=2;
   localparam N = 1 << A_WIDTH;

   input wire clk, rst_n;
   input wire [A_WIDTH-1:0] ain;
   input wire               v;
   input wire [D_WIDTH-1:0] din;
   input wire [D_WIDTH-1:0] bias[N-1:0];
   output reg [D_WIDTH-1:0] ro[N-1:0];

   wire [D_WIDTH-1:0]       d2s    = din + bias[ain];

   integer                  i;
   always @(posedge clk, negedge rst_n)
     if (!rst_n)
       for(i=0; i<N; i=i+1)
         ro[i] <= 0;
     else if (v)
       ro[ain] <= d2s;

endmodule // mux_test

The model-sim gives me the following:

— Compiling module mux_test

** Error: …./mux_test.v(3): (vlog-2110) Illegal reference to memory "ro".

** Error: …/mux_test.v(5): (vlog-2110) Illegal reference to net array "bias".

Best Answer

With Verilog you cannot have an input or output port with more than one dimension - so you can't declare a 2D array to be an input or output.

Instead you need to pack the array into a single dimension which can be done using a generate loop.

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Electronic – How to assign value to bidirectional port in verilog

If you must use any port as inout, Here are few things to remember:

You can't read and write inout port simultaneously, hence kept highZ for reading.
inout port can NEVER be of type reg.
There should be a condition at which it should be written. (data in mem should be written when Write = 1 and should be able to read when Write = 0).

For e.g. I'll write your code in following way.

module test (value, var);
  inout value;
  output reg var;

  assign value = (condition) ? <some value / expression> : 'bz;

  always @(<event>)
    var = value;

endmodule

BTW When var is of type wire, you can read it in following fashion:

assign var = (different condition than writing) ? value : [something else];

Hence as you can see there is no restriction how to read it but inout port MUST be written the way shown above.

I hope that explains it to you.

Electronic – Verilog asynchronous reads of regs – and design question

Your code simulates two multiplexers. These are actually asynchronous components. The fact that Verilog requires data1_temp and data2_temp to be declared as reg's is a quirk of Verilog syntax and your choice of coding style, and doesn't mean these signals would be the outputs of storage elements in a physical implementation.

If you want to capture these values in actual registers, you need to add those explicitly:

reg [7:0] data1, data2;
always @(posedge someclock) begin
    data1 <= data1_tmp;
    data2 <= data2_tmp;
end

But I would like to know what this mini register file would be made of in hardware. Particularly, the 4x8 bit array consisting of k0,k1,k2,k3.

You haven't shown how these variables are assigned, so it's not possible to say how they are implemented. As your code showed, just declaring them as reg doesn't guarantee they are implemented with actual storage elements. If you assign them inside a block that begins always @(posedge clk) then very likely they are flip-flops, but there are ways you could code them that would make them synthesize differently.

I thought when it came to registers and arrays like this, you need a clock to read out data, like RAM?

You need a clock to update a (physical) register. You can read it out at any time. For example:

wire [8:0] sum;
assign sum = k0 + k1;

is perfectly valid code. sum will change whenever any of its inputs changes. If k0 and k1 are the outputs of flip-flops, their values will only change when there is a clock edge.

For another example, you could equally well describe your multiplexers with code like this:

reg [7:0] k0, k1, k2, k3;
wire [7:0] data1_tmp;
reg [1:0] reg1;
// k<n> and reg1 are assigned elsewhere.
assign data1_tmp = (reg1 == 0) ? k0 :
                   (reg1 == 1) ? k1 :
                   (reg1 == 2) ? k2 : k3;

how do I read from this tag_array and do the comparison all within the same clock cycle?

Let me repeat a key point for emphasis: You need to use a clock to assign a new value to a register (an actual hardware register or group of flip-flops). It's output is available at any time.

RAMs are different and how you access the contents of a RAM will depend on details of the type of RAM you use.

I got confused because frankly I don't know enough about memory hardware and how that's possible.

Another key strategy: When you are learning digital logic, I recommend you learn about the physical hardware first, and then work out or study how to simulate it in HDL second. So first, learn what a physical flip-flop is, then learn the standard Verilog methods of describing a flip-flop. Especially if you are trying to write HDL for synthesis, trying to write good code before you learn the capabilities of the underlying hardware will lead you down a lot of dead-end paths.

Best Answer

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Electronic – How to assign value to bidirectional port in verilog

Electronic – Verilog asynchronous reads of regs – and design question

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