Port masking and ports in pic

Assuming you need a read cycle on each port on each clock cycle, each BRAM will give you two read ports. Beyond that, you have to replicate the contents of the memory.

Is the bandwidth required at each port less than the raw bandwidth of the BRAM? In that case, you might consider multiplexing the ports. Use a counter that runs at the full speed of the BRAM to drive a multiplexer that scans the address bus for each port, feed these addresses to the BRAM, and then deliver the data (typically 2 clocks later) to the corresponding data bus for each port.

The downside of this approach is that the access latency for each port is now N clocks longer than the non-multiplexed case. There are various ways to deal with this latency, including adding additional pipeline stages to the other data paths.

Note that with a 2-port BRAM inside the module, you can scan two of the external ports at a time.

I'd recommend that you check the datasheet and see if there are any errata associated with that particular micro.

From what I know (in the past), the case used to be where I would have to read/modify/write and then (in some cases) write twice to a port to ensure that it took.

Aside from that, can you isolate the port to ensure that nothing else is influencing that port pin? If you have a development board with NOTHING connected to that port, it might be worth a try to run the code there and see whether or not it is externally influenced or not.