You seem to be looking for an MCU that has a power failover built in as a peripheral of sorts. There may be a rare MCU available that has this, but from my memory there aren't many in a general way. For instance, I know that Atmel CortexM3s have the ability to run their internal RTC off of battery power. However, that is about as much that you can do.
Instead of looking for a single chip solution, it may be easier to look at designing a low power system out of a few different pieces, which would be easier to do.
For a microcontroller, pick something that's specifically designed to be low power. Having fine grained power control on the peripherals and the availability of low power sleep states is a plus. I've seen TI's MSP430 line qualify well in those parameters. Olin, in his comment, suggests the PIC16F1xxx series. Neither is an 8051 based solution, though. There may well be 8051 based controllers which qualify. I don't know how amenable the 8051 core is to low power states, though to be fair a lot of these other cores also do most of their sleeping by slowing down system clocks and turning off peripherals, which doesn't really need a specialized core.
In order to switchover power, you could use an IC designed for doing that, depending on the sort of battery and topology you have in mind. For a non-rechargeable coin battery sort of thing, you could look at one of the many RTC and Watchdog and Reset controller ICs, a large number of which include some way to switch over to a battery. For a rechargeable battery, assuming its voltage to high enough to be close to the supply voltage you intend to use with mains power, you're better off using a battery tied bus topology. This means that the battery is always connected to the circuit. Imagine the battery and mcu being connected in parallel. When there is mains power, the battery is charged also (using appropriate charging circuits depending on the chemistry of the battery) and when its absent, the current through the battery reverses and powers the circuit.
In general:
Take whatever physical system to an extreme, and all the simple models which were developed by engineers will break apart.
Simple model for active power dissipation:
The statement about an exponential increase in heat dissipation at extreme overclocking is not consistent with the following equation:
$$P_g \propto C_gV^2f$$
but how the above equation was derived?
Well, it is based on the following simplification:
simulate this circuit – Schematic created using CircuitLab
This model assumes that:
- Transistors behave like an ideal, mutually exclusive switches (no overlap in time when both switches are ON)
- All capacitances may be represented as a single equivalent capacitor at the output
- No leakage currents
- No inductances
- More assumptions
Under the above assumptions, you can think of inverter's (or any other logic gate's) action as of charging the output capacitor to \$V_{dd}\$ (which consumes \$\frac{1}{2}C_{tot}V_{dd}^2\$ Watt from the power supply), and then discharging it to ground (which does not consume additional power). The frequency factor \$f\$ is added to represent an amount of such cycles per second.
In fact, it is surprising that the above equation may be an accurate estimation of dynamic power at all, given the huge amount of non-trivial assumptions made. And indeed, this result may be used for the first order analysis only - any serious discussion of power dissipation in modern CPUs can't rely on such a simplified model.
How the simple model breaks:
All the assumptions made while developing the above simplified model break at some point. However, the most delicate assumption which can't hold for an extreme frequencies is that of two mutually exclusive ideal switches.
The real inverter has non-ideal Voltage Transfer Curve (VTC) - a relation between inverter's input and output voltages:
On the above VTC the operational modes of both NMOS and PMOS were marked. We can see that during switching there will be time when both NMOS and PMOS are conducting at the same time. This means that not all the current drawn from the power supply will flow to "output capacitor" - part of the current will flow directly to ground, thus increasing the power consumption:
What this has to do with frequency:
When the frequency is relatively low, the switching time of the inverter comprises negligible part of the total operational time:
However, when the frequency is pushed to the limit, the inverter "switches continuously" - it is almost always in switching activity, thus dissipating a lot of power due to direct ground path for the current (time scale changed):
Maybe it is possible to try to model this and see if the result is exponential, but I prefer to use simulations (however, the simulation will account for all non-idealities, not just this one).
Simulation results:
In simulation I measured the total energy (integral of power) drawn from an ideal power supply by an inverter in the following configuration:
The first and the last inverters are there just in order to model a real driving and loading conditions.
The dissipated energy as a function of frequency:
We can see an approximately linear dependence for periods longer than 1ns, and clearly exponential dependence for shorter periods.
Notes:
- For the simulation I used an antique 0.25um transistor models. The current state of the art transistors are more than x10 shorter - I guess the divergence from the linear model is stronger is newer technologies.
- The question whether a particular CPU/GPU can be overclocked such that it enters the exponential frequency dependence state while still stable and functional is device specific. In fact, it is exactly what overclockers try to derive empirically - to what frequency can a given device be pushed without malfunctioning.
- All the above results and discussions do not consider changing voltage levels. I guess there is no way to analytically predict the outcome of simultaneous change of both frequency and voltage - the only way to find out is to perform an experiment.
From a single inverter to CPU:
CPUs mainly consist of logic gates, which are conceptually similar to an inverter. However each modern CPU has sophisticated measures of controlling its operating frequency, operating voltage and can turn off its submodules during runtime. This means that the heat dissipation trend of the whole processor may be slightly different than this of the single inverter. I guess that the statement about exponential increase in heat dissipation during extreme overclocking is a bit of exaggeration, but we are not mathematicians: either it is exponential, or \$\propto f^{3+}\$ - it is all kind of "bad".
Best Answer
The maximum power dissipation is a rating of how much power the package can physically dissipate. How the MCU ends up drawing that much power is another matter; for instance, it could be simply a lot of GPIO pins each driving substantial output current.
If you want to compute actual power consumption, you should look at the relevant figures in table 10 for power consumption (for instance, IDD(REG)(3V3)), the graphs in figures 11 through 19, and the peripheral power consumption figures in 10.2. Sum up the relevant figures and multiply by the operating voltage to get a figure in watts.