Random-delay gen

capacitordigital-logictransistors

Some years ago I tried to design a circuit where (among other things) a LED flashes after a kinda random delay. As it didn't work, (and after raging and destroying everything that could help me solve the problem) I am wondering if there was a fundamental mistake or I was just too sloppy.

Today, I finally found a print of the circuit (the digital version is lost anyway) so that I, at least, can ask for help.

Picture of the circuit:

schematic diagram

(Hope you're not confused by the european symbols…)

By unplugging the counter IC (7474), everything is working as it should (just with constant delay): by pressing the first button, the belonging LED lights up till the LED "D4" flashes.

Therefore, just the upper half of the circuit is interesting for me. Without the counter IC the delay is generated by the capacitor "C1". My intention was that, by grounding the other 2 capacitors (C2 and C3), the capacity (and the delay time) is tripled.
As the counter IC is supplied with nearly the same voltage as the capacitors, the 2 capacitors (C2 and C3) should only influence the circuit while the counter IC doesn't output TRUE

The outputs of the counter IC should be random, as the counters are set by oscillators (made with IC2)

Best Answer

As the counter IC is supplied with nearly the same voltage as the capacitors, the 2 capacitors (C2 and C3) should only influence the circuit while the counter IC doesn't output TRUE

This is your false assumption. C2 and C3 have the same capacitance, and the same effect on the timer circuit, regardless of whether their negative ends are held at 0V or 5V.

Note that when they are at 5V, you are reverse-biasing the capacitors, which can potentially damage them (but probably not too badly at 5V).