I am trying to build serial-in shift register (non cycled) based on synchronous RS flip-flop, but i'v got a problem with synchronization. My clock generator was configured to long on period and short on period. In first case all flip-flops are setups to value that comes to first flip-flop in scheme (example at first time chart). It's looks obliously, because S-RS is level-triggered flip-flop. In short on period case register gives right result exclude one case (between 20ns and 25ns on second time chart).
Are there ways to solve this problem, without changing or adding a flip-flop than that used in the scheme?
Shift register on sync RS flip-flop
flipflopshift-registersynchronous
Related Solutions
The two flip-flops are used to avoid issues with metastability. The idea is that the first flip-flop has some small probability of going metastable, but if it does, it's much less likely that the metastable state will propagate to the second flip-flop.
A "hardened" flip-flop has higher internal gain than an "ordinary" flip-flop, which means that a metastable state should decay more quickly, reducing the chances of propagation. However, I've only ever seen "hardening" discussed in the context of custom IC design, and I'm not aware of hardened devices that are available as discrete devices.
Putting a delay between the flip-flops is actually counterproductive, as this would reduce the window of time for the metastable state to decay.
So, just use two flip-flops of whatever technology best fits in with the rest of your circuit.
There may have been a wire in the wrong place or something. I did have it spread across three breadboards. I sketched everything out in a schematic, then pulled all the wires out and started over, following the schematic. Then things worked! Here's the schematic I used. The LED only lights up once the D input to the first flip-flop has gone HIGH and then LOW, which is how it should work.
Related Topic
- Electronic – is flip flop a synchronous or an asynchronous sequential circuit
- Electrical – Difference between D-Type Flip-Flop and Edge-Triggered D-Type Flip-Flop
- Electronic – Understand the timing of Shift Register
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Best Answer
I believe your problem comes from the clock signal you're using. Its positive pulses last for about 100 ps or less, and the flip-flops probably don't have enough time to react to them, which leads to sporadic errors.
Find the maximum switching frequency in the spec of your flip-flops. It is usually given for a clock signal with 50% duty cycle, so you can take half of the period and assume that positive pulses of your custom clock signal cannot be shorter than this value.