digital-logicseriesshift-register
If we have for example 3x16bit shift registers connected in series, can we clock 48 bits of data through one shift register at once and then latch all of them to output data registers, LATCH CLK and OE pins are shared.
If my thinking is not right, please explain how data clock works when shift registers are in series.
If I may answer my own question. It should work. Here's how with arduino over SPI.
void setup() {
//Setup SPI
SPI.begin();
//Setup CD4021
pinMode(CD4021_PSC_PIN9, OUTPUT);
digitalWrite(CD4021_PSC_PIN9,HIGH);
//Setup 74HC595
pinMode(HC595_LATCH_PIN12, OUTPUT);
digitalWrite(HC595_LATCH_PIN12,HIGH);
}
void loop(){
//Shift out to 74HC595
digitalWrite(HC595_LATCH_PIN12,LOW);
SPI.transfer(BYTE_DATAOUT);
digitalWrite(HC595_LATCH_PIN12,HIGH);
//Shift in from CD4021B
digitalWrite(CD4021_PSC_PIN9,LOW);
BYTE_DATAIN = SPI.transfer(0x00);
digitalWrite(CD4021_PSC_PIN9,HIGH);
}
Learned from here, from someone who has done this exact implementation before.
Refer to the datasheet (better if you provide a link to the datasheet you're consulting in your question, but from the colors I assume it's NXP).
This particular shift register has an input latch as well as the PISO shift register. Some (eg. 74HC165) don't have the input latch.
In answer to your questions:
1) When you are shifting the shift register, something will get shifted into the serial input. That pin allows you to choose to shift in logic '0', '1', or perhaps cycle the contents around, or whatever else you choose.
2) Rising edge on SHTP clocks the shift register.
3) Rising edge on STCP loads the input latches from the inputs.
Note a low level on /PL loads the shift register from the input latches. If /PL is low, then a rising edge on STCP loads the shift registers from the inputs.
/MR resets the shift register (not the input latches) and it is considered 'invalid' to have /MR and /PL active at the same time.
Best Answer
You are correct. So long as the Dout of the first shift-register is routed into the Din of the 2nd, and then from 2nd into 3rd, and as you say have Latch, Clock & OE of all 3 connected together & into your MCU (or whatever you're driving them with), then you can clock in 48 bits, and then latch & OE them all at once. What ever was in the 3 registers originally 'disappears' (virtually 'falls out the end' of the 3rd shift-register's Dout pin) SO LONG as you clock in all 48 bits.
Alternatively, you can choose not to clock all 48 bits, for example in a LED display - with this technique you can achieve 'sliding' effects without having to re-clock all the 48 bits (followed by Latch & OE) over & over. You can clock just a single new bit in (which pushes the 48th bit out the far end never to be seen again), and then whatever was originally in the 48 bits shifts over 1 bit - whatever 'pattern' that might be shifts over 1 bit, & a new bit is added. I'm probably not explaining it very well, but just give it a try, you can't hurt anything :)