I have done few BLDC motor controllers with trapezoidal modulation and they work fine. Now i'm trying to build another one with space vector modulation but as it doesn't work well i'm getting more and more confused.
I have 3 PWM signal pairs (total of 6 signals) driving 3 phase integrated FET driver. What i need to know is how exactly should the 6 PWM signal waveforms look like for a space vector (SV) modulation. Nearly all the SV images in internet show only the 3 signals and i am not certain what they are exactly (phase output, high or low control signal?).
The first question is:
Should the high and low PWM signals of one leg be inverted with each other? In other words – should one of the leg signals always be active (active = FET conducting) ? Of course some dead-time is needed.
This solution didn't work well because both motor and driver got very hot even at low speeds. Maybe i have something else wrong, but if i just theoretically think of this (and look at signals with logic analyzer) then some things doesn't make sense.
Let's say i want to have low duty cycle (10%), then according to SV PWM all 3 low side FET's are ON (conducting) most of the time. But that means the motor is actually braked (slow decay)!
It really confuses me because this logic means that polarity of each phase is swapped on every PWM period. Also – with trapezoidal modulation one leg is always undriven (high and low FET are both off), but that's not the case in SV. Or do i need very high PWM frequency to get smooth output? I'm using 16 kHz because driver can't handle more by spec.
Then i did an assumption that if SV phase should be positive then i pulse the high side PWM signal and keep low side inactive. And if phase should be negative then i pulse low side PWM signal and keep high side inactive. My theory was that the motor should free-wheel when doing like that. But it didn't work well. Also i suspect in such way the inducted current flows through body diodes…
Anyway, i don't want to just try. I'd like to know which way is correct and then continue the development process.
Best Answer
SVM provides means to derive the "voltage" which should appear at phaseA, phaseB, phaseC. HIGH == full +DC, LOW = full -DC.
What is usually missing in such papers and descriptions is the final block - the commutation block. This block takes these phase signals and generates the required PWM for the upper and the lower switching device AND the deadtime during the transitions.
You are correct that essentially the actual drive signal are the compliment of each other WITH some interlock logic.
Output = HIGH => UpperSWT = ON, LowerSWT = OFF
Output = LOW => UpperSWT = OFF, LowerSWT = ON
Output = HIGH-LOW => UpperSWT = turnOFF, LowerSWT = delayed TurnON
Output = LOW-HIGH => UpperSWT = delayed TurnON, LowerSWT = turnOFF
Have a read of this paper I co-wrote. There is some PWM signals to the end
https://drive.google.com/file/d/0BxW4BDaqkIc2RDVBcnItcXJoQWZ0LVN4S2JQcW9uUHVKZkJZ/view?usp=sharing