Spartan 6 FPGA IO changes state disregarding design

fpgaport

Hello I have made Spartan 6 board and now I'm trying to get it work, I have successfully managed to get programming of SPI flash working so I can upload bitstreams, but I have problem that some of IO pins doesn't stay at their desired state.

For example I have 4 IO used to control relays of attenuators (used in oscilloscope module) and when I set state at reset it holds it for 40 nanoseconds and then it gets back to zero.. I even have communication protocol in which I can set IO state programatically through software and it change state but again only for 40ns or so then go back to logical zero.

In simulation everything works as expected, also post par static timing shows that my timing constraints (60MHz clock of FTDI's FT245 and 150MHz clock of ADC oscillator) were met. I have triple checked my UCF if I have not used wrong pins but it's all the same.

I was thinking that I am somehow reseting design (I use FTDI for that) in FPGA but it's not the case because I have hooked scope on reset pin of my design and it didn't triggered. Also other things in my design works, for example I can successfully set reference voltages of ADCs (controlled by DAC) values through serial interface (which is slow – 100kHz) so reset that would kill IO state after 40ns would also stop setting of DAC.

Do you know what could force FPGA to disregard design set IO states?

//edit: adding code:

this is part that sets IOs: (the led1 faintly blinks when this happens)

              when SET_ATTENUATORS =>
                led1 <= '0';
                adc1relatt <= commandData(71);
                adc2relatt <= commandData(63);
                state <= IDLE;

and this is IDLE state:

             when IDLE =>
                ft245rw <= '0';
                ft245strobe <= '1';
                ft245dataWaitIn <= '0';
                if (to_boolean(ft245busy) and (ft245oe = '0')) then
                    state <= READ_COMMAND;
                    ft245strobe <= '0';
                else
                    state <= IDLE;
                end if;

and this is reference voltage setup state:

              when SET_VREF0 =>
                led1 <= '0';
                dacVrefTopA <= commandData(72-1 downto 64);
                dacVrefBotA <= commandData(64-1 downto 56);
                dacVrefTopB <= commandData(56-1 downto 48);
                dacVrefBotB <= commandData(48-1 downto 40);
                if to_boolean(dacBusy) then
                    dacStrobe <= '0';
                    state <= SET_VREF1;
                else
                    state <= SET_VREF0;
                    dacStrobe <= '1';
                end if;
            when SET_VREF1 =>
                if to_boolean(dacBusy) then
                    state <= SET_VREF1;
                else
                    state <= IDLE;
                end if;

In this state the led1 also only faintly blinks (it should stay on, not blink) but also only other state that I change state of LED is reset which couldn't happen because that reset would also reset DAC module which would prevent DAC setup module from setting DAC values (it successfully does that).

Best Answer

I finally found that problem was that I have been loading the same design over and over.. So I thought that I have design that light the led but there was none.. Now it works as expected. because I thought that *.MCS files are generated only once not that I have to generate MCS file from BIT file every time I change bitstream.. now it is working, my problem now is that some of packets doesn't go intact through FT245.. I'll make simple acknowledge protocol to fix that.