One reason to divide a clock by two is to obtain an even 50% duty cycle square wave. It may be that the 8085 internally uses both clock edges, and wouldn't function if one half of the cycle happened to be much shorter than the other.
In the days when the 8085 was new, those nice canned oscillators weren't common, and people often cobbled together clock circuits out of discrete crystals, capacitors, and logic gates. Dividing by two ensures that you have equally spaced rising and falling edges.
As for 6.144MHz, you will find that it can be divided by an integer to get common baud rate values, at least up to 38400.
follow up ...
Looking at an Intel data sheet for the 8085, there are three interesting statements
The 8085 incorporates all of the features that the 8224 clock generator and 8228 system controller provided for the 8080A
X1 and X2: Are connected to a crystal, LC or RC network to drive the internal clock generator. The input frequency is divided by 2 to give the processor's internal operating frequency.
CLK: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.
So, speculations about using the odd edges of the clock to move stuff around internally aside, it becomes apparent that when they designed the 8085, Intel was replacing the need for a special clock controller by integrating that feature into the chip. Dividing the X1-X2 timebase in half before outputting it as CLK ensures that the system gets a nice even duty cycle, if nothing else.
The \$3\$ machine cycles are:
- Opcode Fetch Cycle
- Memory Read Cycle
- Memory Write Cycle
Internally, depending on the opcode, each machine cycle takes from \$3\$ to \$6\$ T-cycles (or T-states) to accomplish the \$1\$ machine cycle.
T-states are one clock period long, and the instruction length is measured in T-states.
For example, a typical Opcode Fetch has \$4\$ T-states: the first \$3\$, T\$1\$-T\$3\$ are used to fetch the instruction, and T\$4\$ is used to decode it.
Instruction cycles take from \$1\$ to \$6\$ machine cycles.
The 8085 also has some external status pins that can be used to identify which machine cycle it is currently in. These are the \$\mathrm{IO/\overline{M}}\$ signal, the \$\mathrm{S0}\$ and \$\mathrm{S1}\$ signals.
Opcode Fetch: \$\mathrm{IO/\overline{M}} = 0,\$ \$\mathrm{S0} = 1\$ and \$\mathrm{S1} = 1\$
Memory Read: \$\mathrm{IO/\overline{M}} = 0,\$ \$\mathrm{S0} = 0\$ and \$\mathrm{S1} = 1\$
Memory Write: \$\mathrm{IO/\overline{M}} = 0,\$ \$\mathrm{S0} = 1\$ and \$\mathrm{S1} = 0\$
There is also I/O read and write cycles, which are not part of this DCR M instruction, but when those cycles are active in other opcodes the control/status pin \$\mathrm{IO/\overline{M}} = 1\$
Best Answer
A time cycle is one tick of the core CPU clock. A machine cycle is what the internal state machine of the CPU is doing at the time.
This document explains it all in detail
Basically the machine cycles are:
The first one, Opcode Fetch, is described as:
... continued later ...
... and another good snippet that describes the relationship more ...
So that machine cycle takes 4 (minimum) time cycles.