If the title is off putting, I will elaborate.
Some say that if you want a custom CPU you can "customize" it with a field programmable IC, AKA, field programmable gate array.
But to what extent? And is over and under clocking, address line modding, register-level-transfers, and other features able to customize?
For example, one would expect a FPGA to enable "changeable", but changeable in the sense that it can be optimized for a specific purpose, speed, and system?
Like, if I want an FPGA to be customized to replicate an old video game system I would expect it to have a slower clock, less bit width, and to access slower DRAM.
Can FPGAs really be customized for a wide variety of uses, either under clocking and lowering performance, to over clocking and extending to maximum processing power and I/O lines, etc.?
Best Answer
An FPGA contains certain resources, like flip-flops, programmable look-up tables (which can be configured to replicate the function of logic gates), block memory, and high-speed i/o transceivers. These resources are connected by a mesh of interconnect wires, which can be programmatically connected to the other resources.
You can configure the FPGA for your use exactly to the extent that you are clever enough to figure out how those resources can be used to produce the function required for your use.
This is somewhat simplified by the ability of synthesis tools to figure out how to allocate those resources when given a higher-level description of the function in a hardware description language (HDL). However even with the help of synthesis tools, a good FPGA designer will structure their code with the underlying resources in mind in order to maximize the functionality they can obtain from a given FPGA.
As others have said, there is generally a maximum clock frequency that a given FPGA can achieve. And the FPGA can generally operate from 0 Hz up to that maximum frequency.
What hasn't been mentioned yet is that the maximum frequency is only achieved when the combinatorial logic between one flip-flop and the next has a certain limited complexity, and when the design overall leaves enough resources free to give the design tool freedom to optimize the interconnects with a reasonable amount of computational effort.
If too-complex logic is used between flip-flops, or if the resources are highly utilized (say, more than 70% utilization) you'll likely find that the maximum frequency for your design is substantially less than the ideal maximum frequency for that FPGA.