In VHDL, is there any way to convert an integer
into bit_vector
of length of 14?
Currently, I am first converting the integer
into std_logic_vector
and then into bit_vector
.
for i in 0 to 5 loop
x_std(i) <= conv_std_logic_vector(x_int(i),14);
x_bit(i) <= to_bitvector(x_std(i),14); --here comes error
end loop;
In behavioral check syntax, following error comes while converting std_logic
into bit
:
Type bit does not match with the integer literal
I am using following libraries, ieee.std_logic_1164
, std_logic_arith
and std_logic_unsigned
.
How can I do this conversion without an error?
Best Answer
To answer your specific question: the
to_bitvector()
function fromstd_logic_1164
only takes one input, a signal of typestd_ulogic_vector
orstd_logic_vector
. If you search for the function name you find documentation like this which gives the interfaceSo change your code to this and it should work (though I haven't tested):
As to why the functions take different inputs, the
conv_std_logic_vector
function requires a length parameter as theinteger
type has no specific length. The length parameter tells the synthesiser how wide astd_logic_vector
is created by the function. VHDL is strongly typed and the length of the signal returned from the function is then checked against the left hand sign on the assignment (x_std(i)
) to ensure they match.Conversely, the
to_bitvector
function simply goes through each element of the array in turn performing a mapping fromstd_logic
tobit
and the returned array width is therefore defined by the width of the input array.It's also worth looking into using VHDL attributes as the length input to conversion functions. This code won't break if you decide to change the width of
x_std()
andx_bit()
later: