Understanding D flip flop function – what this thing does

Try starting to think from the second line.

If you put 0 to S port, it would go to 0 in the output regardless of the other input because it is an AND port. But its output is inverted since it is and NAND port, so when you put 0 in S signal, its output will necessarily goes to 1 regardless of the other NAND input.

Therefore, one of the lower NAND port inputs will be 1. Since we are in the second line of the truth table, R should be 1. So the lower NAND port will have both inputs in one (H). So its output will necessarily be zero. Then you have Q = 1 and Q! = 0.

If you make the same reasoning for the third line, you get correct results since it is the symmetrical situation.

As for the first line, you cant have correct results. Note that if we put 0 to S, we have Q = 1 (as the second line of the table). Altough if you put zero to R too, you will also have Q! = 1. This situation is called disallowed because Q should complement Q!. They always have to be different signals.

And for the last line, imagine we are in the second line again so we have Q = 1 and Q! = 0. If we put S to 1 (it was zero before), note that Q! is already zero, so changing S signal will not change the first NAND port result. So whenever you are in states 2 or 3 (second or third line), placing 1 to any of the inputs that are low, will not change the state.

Z means high impedance = "disconnected from the wires" This is the 3rd alternative to 0 and 1 in 3-state outputs. It's used to enable several devices to output their data to the same wires in their turns. 3-state outputs are the basis for the data buses in the computers.Output enable =0 disconnects the device. The red blocks are the 3-state capable buffers. They sometimes have enhanced long line drive capability, Standard logic family members do not have that capability unless otherwise stated in the datasheet.

The dual clock input D-like flip-flops (green) are not full D type flip-flops because they need a clock pulse and the same as inverted. The one inverter delay may have some role in its function. Anyway the resulted function is the same as a chain of D -FFs. The symbol is not standard. It follows manufacturers own conventions.

As commented already, one black connection dot is missing from the clock pulse distribution.

The upper row (blue) is a battery of D latches that keep the data stable when the lower battery is shifting its content to the right.

Latches are not triggered at the edge. Their outputs follow the D-inputs as long as the Strobe=1. The outputs freeze when the Strobe is swicthed to 0.

This IC is used to convert serial data to parellel and also to store one byte that is received one bit at a time from the serial input. Several IC:s can be chained.

This IC is still useful to expad the output capability of a microcontroller. Three of these chained give 24 outputs that need only 3 outputs from microcontroller. In many applications it's not harmful that the outputs can be updated quite sparsely, maybe only once in a millisecond.