If you're not too concerned about the effects of self heating, then a circuit like the one shown in fig. 1 might be useful.
simulate this circuit – Schematic created using CircuitLab
Figure 1.
Resistor R1 is the current sense resistor. If you know R1's resistance value (by measuring its resistance with an ohmmeter), and if you measure with a voltmeter the voltage drop across R1, then you know via Ohm's law how much current is flowing through R1 and through the diode (the "device under test" (DUT)).
Measure and record resistor R1's resistance value.
The desired current level is set via potentiometer R2.
Using Ohm's law, calculate the voltage drop across current sense resistor R1 that corresponds to the desired test current:
$$
V_{R1(TEST)} = I_{TEST} \times R1
$$
Connect your voltmeter across R1 (position VM1) and adjust R2 until the voltmeter indicates \$V_{R1(TEST)}\$ volts.
Disconnect your voltmeter from test position VM1 and reconnect it across the DUT (test position VM2). Measure and record the voltage across the DUT.
Repeat this procedure for additional test currents of interest.
A slightly more sophisticated test circuit is shown in fig. 2.
Figure 2.
Op amp U1A and its surrounding components comprise a transconductance amplifier circuit—i.e., voltage in, current out. The amplifier's input voltage range is 0V to 5V and output current range is ~0mA& to 100mA.
The desired input voltage value is set by potentiometer R2. Use a voltmeter connected between test point TP1 (+) and ground (-) to set the desired input voltage when adjusting R2. (Hint: If R2 is a 20-turn pot you can get good resolution when setting the input voltage.)
The transconductance amplifier circuit's output current is approximately
$$
I_{OUT} \approx \frac {V_{TP1}}{50\,\Omega}
$$
The \$50\,\Omega\$ resistance is the equivalent resistance of the four parallel resistors R3 through R6. This \$50\,\Omega\$ resistance must dissipate about 0.5 Watts of power, so putting four \$200\,\Omega\$ 1\2 Watt resistors in parallel distributes this power dissipation across four resistors. The goal here is to reduce the level of self-heating in the \$50\,\Omega\$ load and thereby keep its resistance value more-or-less constant.
An op amp typically cannot source or sink much current (perhaps only a few milliamps); therefore, transistor Q1 is needed to amplify the op amp's output current to the desired test current levels (tens of milliamps or more).
To test the diode, start by choosing the desired test current value—e.g., 1 mA. Calculate the voltage at test point TP1 that corresponds to the chosen test current:
$$
V_{TP1} = I_{TEST} \times 50\,\Omega = (1\,mA)(50\,\Omega) = 50\,mV
$$
Connect the voltmeter between test point TP1 (+) and ground (-) and adjust resistor R2 for an indication of 50 mV on the voltmeter.
Disconnect the voltmeter from test point TP1 and reconnect it across the diode at test points TP2 (+) and TP3 (-). Measure and record the voltage drop across the diode.
Repeat these steps for any additional test currents of interest.
For the schematic shown in fig. 2 I performed a DC sweep simulation that adjusts parameter POTSET from 0 to 1 (0% to 100%), which equates to adjusting potentiometer R2 from its minimum value (0 ohms) to its maximum value (5 kohms). Figure 3 shows the simulation results, plotted with the diode's forward current (y-axis) versus its forward voltage drop (x-axis).
Figure 3.
Caveat
I have designed (circa '99) integrated micro KOPIN LCD displays to display VGA and VCR signals, yet I have no experience with your monitor, but I recognize the blooming effects.
LCD simple Theory of Operation
We know the pixels are addressed in a matrix of rows and columns with the pixel clock, but the analog characteristics are refreshed as a differential charge voltage at some bias voltage defined as a White (W) level DC Restorer circuit. It switch clamps each signal momentarily during the horizontal blanking interval to this V_w level.
Each video signal must be AC coupled to do this. ( Verify) or else DC bias exactly to the differential voltage specs in a range within the Analog voltage.
The bias level enables a polarized dielectric to hold a charge with low leakage in between the White and Black levels defined by internal voltages. Otherwise leakage currents decay the black to white and covering the screen with fog starting around the edges. A black signal would look like large pulse signals ||______|| in both polarities.
A white signal will look like small pulse near the blanking interval values.|_----------__--- ( not exactly)
When the DC restore circuit stops working or clamps on inverted differential signals ( verify) or puts the applied charge where it causes the overall voltage reference to be wrong, then it starts to bloom around the edges as in your video.
But since you have not even a ghost of any test patterns , it may be a simple problem. Perhaps you can verify the analog signals to be valid then the clocks for pixel clock , V sync, H sync pulses are valid etc or the chip is biased wrong.
Best Answer
The resistance between Rin and Lin will be R5 + R6 + R7 + R9
The resistance between Rout and Lout will be R5 + R6
The resistance between either input and its output will be R7 or R9 (which I'd expect to be the same)