Does anybody have a reference to an in depth explanation of hardware implementation of CORDIC algorithm for sine/cosine calculation? I'm looking for a way to model it in Verilog on structural level. I was able to do it on behavioral level, but when code got synthesized, I got way to many gates, so now I want to optimize the design by describing it structurally. I would appreciate any help.
Verilog structural CORDIC implementation for sin/cos calculation
cordicverilog
Best Answer
As Chris suggested, the best would be to use a macro provided by the technology vendor. Otherwise, you would need to study alternative structures for implementing a CORDIC core.
From your description of having too many gates, you might just be using an architecture that is not suited for hardware implementation.
Your Verilog model needs to be based on hardware building blocks (RAM, multipliers, logic) instead of software algorithms. HDL synthesis tools do not magically convert algorithms to hardware blocks efficiently.