I want to convert a verilog netlist into a simulatable SPICE (or HSPICE) format. I have seen people talking about verilog-In and spice out in Cadence. How does this process actually work? What are the tools I should use?
I can also access synopsys tools. If you know how to use synopsys tools to achieve the same purpose, that will help too.
Best Answer
This is not a trivial process, but it does indeed work. You need to have a synthesis library for the specific integrated circuit process that you intend to use, as well as a corresponding SPICE simulation library and SPICE process models for the IC process. Synthesize your Verilog to a gate-level netlist using the synthesis library of the target process. Convert the Verilog gate-level netlist to a SPICE gate level netlist (they are both just text, it's a simple syntax conversion). When you run SPICE, inlude the SPICE library for the gates and the SPICE models for the process. If you want to include the effects of wiring then you need to generate a transistor level layout and extract the parasitic capacitances from that...also a non-trivial process.