VHDL: Simulating Delay for ISE UNISIM components

isemodelsimsimulationvhdlxilinx

I have extracted VHDL source of my design from Xilinx ISE.
It uses UNISIM library to model Look-Up Tables and Flip-Flops and other components.
When I simulate my VHDL design (a combinational circuit) using ModelSIM, there are no delays displayed in simulated WaveForms.
I want to know how can I add delay to elements of UNISIM library and then see its effect on MODELSIM simulation?

Best Answer

Each synthesis step generates it's own simulation model. So start start place&route and select 'generate post par simulation model' afterwards. Now you can launch your selected simulator iSim or vSim from ISE.

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