Wikipedia’s definition of DIMM says:
Most DIMMs are built using "×4" ("by four") or "×8" ("by eight") memory chips with nine chips per side; "×4" and "×8" refer to the data width of the DRAM chips in bits.
So if DRAM chips have 8 bit data width why DIMM has 64 bit data width? I mean doesn’t memory controller issue read or write request to one DRAM chip at a time? If it does what is the purpose of other 56 bits?
Best Answer
doesn’t memory controller issue read or write request to one DRAM chip at a time
No, it issues the same address to all the chips at once and gets 8 bits from each of the chips (plus another 8 if it's ECC). This 64 bit chunk is then stored in a cache line.