Why is current going towards the voltage source in this circuit

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You can see that Is was labeled as going towards the voltage source when doing KCL at node a. Can someone tell me why? Is it not supposed to go into the node?

Best Answer

It is just by convention.

If you draw all the currents as either going out of a node (or into a node) a node you can say:

The sum of all currents going out of a node are equal to 0

Obviously then some of the current will have negative values if they are infact flowing into the node, but this way you can do the maths more easily.