Am I correct to assume that the overall circuit will only draw 1A from the power source, but 25% of that power will be dissipated as heat by the voltage regulator?
A linear voltage regulator works in the way described in the question. Switching regulators work differently, described further down.
The regulator draws current from the power supply, 1 Ampere in the example plus some marginal operating overhead of the regulator itself, and power dissipated by each load is calculated by P = I2 x R, or P = V x I, or P = V2 / R, whichever is more convenient to calculate. In this case, as current through elements in series is equal through each element and the combination, and the voltages are known:
- Pload = 6 * 1 = 6 Watts
- Preg = (8 - 6) * 1 = 2 Watts
The first problem I am seeing with this setup is that my power source is under the rated input voltage
A type of linear regulator known as a Low Drop Out (LDO) regulator is designed to work with lower voltage headroom. One of those should be used instead of the 7806, although in practice, most 7806 regulators will actually function even with 2 Volt headroom - Regulation quality may suffer, i.e. it may "drop out of regulation".
The other option I found is to use something from the RC world called a UBEC.
Standard UBECs are actually switching regulators or buck regulators. The way these work is, a high frequency oscillator "switches" the supply voltage on and off, this oscillating voltage is transformed up or down using either inductors, magnetic or piezoelectric transformers, or possibly in some other way, and then rectified and smoothed out to deliver the desired output voltage, in a method akin to using PWM to regulate "effective" current or voltage.
A switching regulator thus does not waste power proportionately to the voltage difference between input and output. Instead, this technology delivers anywhere from 80 to 93% efficiency, since the voltage that needs to be "reduced" is not being dropped across a resistive load at all.
In other words, a nearly constant 7 to 20% (design-dependent) of the final output power is the overhead that appears as heat and inaudible vibration at the switching regulator.
Yes, an UBEC can be used for the purpose described, or a "DC-DC buck regulator module" can be sourced from sites like eBay, often for much less than an UBEC, and possibly with better performance.
Heat generated at the regulator will be less than for a linear regulator, at the mentioned operating load.
This is a linear regulator, not a switching regulator, so you should not see pulsations.
Other than that, your understanding is fairly accurate. The TL431 will draw more and more current through the cathode as the voltage on the sense terminal exceeds its internal reference voltage of about 2.5V. The MOSFET is wired as a source follower, so it has a voltage gain of about 1. C2 is there to make sure the feedback to U1 is not unduly delayed, which could cause oscillation.
So U1 will maintain the voltage at the gate of Q1 in order to have the divided output voltage (R3/R4/C2- node) equal roughly 2.5V.
Because Q1 is used as a source follower, this regulator will not be low drop-out, however it's much easier to assure stability with various load capacitances because Q1 is not adding voltage gain. There is also a lower limit on output voltage of ~2.5V- achieved when R2+R3 = 0 ohms.
Best Answer
Let's check output impedance (top plot) and PSRR (bottom plot) of both PNP and NPN pass transistor versions of this regulator.
Left (NPN) in blue ; right (PNP) in red ; 3 output current steps (1mA,20mA,50mA).
In both circuits the pass transistor (Q5 or Q10) acts purely as current gain. It is not a voltage follower, even in the NPN case, because its input voltage is not controlled, coming from the meeting point of two collectors.
Therefore the circuit dumps into the load a current that is the product of hFe of the pass transistor, multiplied by gm of the input stage, multiplied by error voltage at the input of the LTP, which is the error voltage at the output times the voltage divider ratio. So the DC open loop transconductance is...
Which gives a product of 1.2S as transconductance for the whole circuit. Output impedance is the inverse: 0.83 ohms, which is quite close to the "around one ohm output impedance" on the plot.
This is quite high, for good regulation you need lower output impedance than this so this isn't an acceptable LDO: it doesn't have enough open loop gain.
Let's substitute BJT pass transistors with FETs.
This simple change reduces output impedance by orders of magnitude, at least at low frequencies. This is due to the FET having no DC gate current so at low frequency its current gain is much higher than the hFe of a BJT. The formula to calculate output impedance is the same as above, but with the FET's much higher current gain, transconductance is much higher and thus output impedance is much lower.
Not everything is well and good though, because between 10k-1Meg the output impedance is inductive and that's where we want to cross over with the output cap, so it will probably be underdamped and be a special snowflake LDO that requires an output cap with just the right ESR for damping.
The circuit is an OTA (output transistor included): its output current is proportional to the error voltage at the output, and the proportion factor is transconductance. Since transconductance is dIout/dVout and output impedance is dVout/dIout, one is the inverse of the other.
In the document you linked, the SiC regulator uses collector resistors in the input stage instead of a current mirror. So the input stage doesn't output a current, it outputs a voltage, and the pass transistor doesn't act as pure current gain, instead it's a follower. So loop gain calculations are different.
In the question (and in the linked document) loop gain and transconductance are only studied at DC, ie "0 Hertz". Plotting output impedance versus frequency shows that it rises at a slope of 20dB/decade, just like the impedance of an inductor would.
This is due to the main pole, which is due to input capacitance and Miller effect in the FET pass transistor. This FET is driven by current from the current mirror, and this current is integrated into a voltage by its input capacitance. This creates a pole and loop gain decreases by 20dB/decade.
To understand frequency dependent effects I feel the following analogy works well:
If you drive the device with a current (from I1, having DC and AC components) then this current is integrated into an AC voltage Vgs by the input capacitance. Vgs then drives the output current through the device's transconductance gm. Current gain can be defined just like for a BJT: drain current divided by gate current, and in this case it decreases by 20dB/decade with 90° phase lag.