4 bit mux input/outputs

The best way to get a proper understanding is to write down the truth table completely. You have 3 inputs (A, B, S), so this will give you 2\$^3\$ = 8 combinations:

S  A  B | S' C  D | Z
--------+---------+--
0  0  0 | 1  0  0 | 0
0  0  1 | 1  0  0 | 0
0  1  0 | 1  1  0 | 1
0  1  1 | 1  1  0 | 1
1  0  0 | 0  0  0 | 0
1  0  1 | 0  0  1 | 1
1  1  0 | 0  0  0 | 0
1  1  1 | 0  0  1 | 1

It's often useful to add intermediate results to make things more clear. I added a term \$C = (A \land S')\$ and \$D = (B \land S)\$. Now it should be clear that \$Z = (C \lor D)\$.

I am not sure about the 'lenient' part, but for the "load signal", you've misinterpreted the sense of "load".

In this case it doesn't mean "electrical load" or "resistive load" -- rather it is "the signal that 'loads' the value of D into the memory."

Taking a shot at 'lenient': this may mean that it does not have oscillation problems between the input and the output when connecting it this way. A bad situation would develop if during a transition there is enough delay and enough gain between the input and output that a self-sustaining oscillation develops. But it is not a term I'm familiar with in this context.