4-to-10 Decoder truth table

I'll try to cover the parts of your question separately.

Multiplexing

Is the multiplexer represented in the schematic where it says "buffers"?

Nope! The multiplexer is the select digit part of the circuit. As you said, a multiplexer is an electrical switch: if I have \$n\$ "selector" inputs, I can choose from \$2^n\$ outputs. In your case, you have a two bit counter (because 1 bit isn't enough to count up to 2) which is connected to the "select" part of the multiplexer. The mux then sets one of its four outputs high, depending on what the counter is. If you make your counter reset as soon as it hits 3, then your multiplexer will set 0 high, then 1, then 2, and repeat this loop forever.

If the ultimate goal is to display the output on two additional displays, why couldn't we just wire the all the a's, b's, c's, etc. together?

When the mux has set digit 0 high, we only want to light up display 0 (and likewise for 1 and 2). If you wire the displays together, you can't control them all with different digits.

High End Digit Driver

The purpose of the transistor drivers are to supply/sink current to/from the LEDs, but it's unclear to what it's connected to electrically in terms of the emitter, collector, and base.

Look at a single digit driver. When its mux output is high, you want current to flow from your power supply into the LEDs; when the mux is low, you want to block that current. That means your which digit? output is probably connected to the base of the transistor, and setting it high allows current to flow from the collector to the emitter. Is that enough of a step in the right direction?

If the drivers are simply sourcing or sinking current, why are they connected to the multiplexer?

You'll have three drivers. You only want to turn on one at a time, and the multiplexer picks which one. They aren't "simply sourcing current", I guess - they're current sources that you can selectively turn on and off.

Counter Circuit

However, what is considered a desirable output here?

You want to count

0, 1, 2, 0, 1, 2, ...

so you'll need two wires (like I mentioned above). What parts do you have access to? What kind of counter circuits have you seen before?

As Nedd mentioned, you have a good oscillator set up - that'll be the input to your counter. Flip-flops would be a standard approach from there.

I think it's a poor problem to begin with, because it's not very clear what the overall purpose is and is generally not uniquely solvable as BlueSky has pointed out.

$$\begin{array}{ccc|ccc|ccl} a & b & c & e & c & d & H & & \\ \hline\hline 0 & 0 & 0 & & 0 & 0 & 0 & & \\ 0 & 0 & 0 & & 0 & 1 & 0 & & \\ 0 & 0 & 1 & & 1 & 0 & 0 & & ⬅ \\ 0 & 0 & 1 & & 1 & 1 & 1 & & \\ 0 & 1 & 0 & & 0 & 0 & 0 & & \\ 0 & 1 & 0 & & 0 & 1 & 0 & & \\ 0 & 1 & 1 & & 1 & 0 & 1 & & \\ 0 & 1 & 1 & & 1 & 1 & 1 & & \\ 1 & 0 & 0 & & 0 & 0 & 0 & & \\ 1 & 0 & 0 & & 0 & 1 & 1 & & ⬅ \\ 1 & 0 & 1 & & 1 & 0 & 1 & & \\ 1 & 0 & 1 & & 1 & 1 & 1 & & \\ 1 & 1 & 0 & & 0 & 0 & 0 & & \\ 1 & 1 & 0 & & 0 & 1 & 0 & & \\ 1 & 1 & 1 & & 1 & 0 & 1 & & \\ 1 & 1 & 1 & & 1 & 1 & 1 & & \\ \end{array}$$

This is both truth tables side by side, i.e. left-hand side $$e = G(a,b,c)$$ and right-hand side $$H = F(e,c,d)$$

Now, it's immediately obvious that F couldn't be a simple gate, i.e. not a 3-input and, or, nand, nor, xor, not xor (biconditional), because some lines where H = 1 contain zeros, e.g. line 7.

Now, looking at the table some more, most of the time, H = F(e,c,d) = c. In fact, only two lines don't show this behavior, which I marked with ⬅.

Now, the marked lines appear only once with not c and every where else they're c. This means the difference must be in the e input to F in those lines, i.e. e must be 1 for both groups of lines and 0 for all others or vice versa. The choice of which lines have e = 1 and which have e = 0 is arbitrary, hence the solution to this problem is not unique. Notice that groups of two lines share the same e, because the inputs to e = G(a,b,c) are the same.

$$\begin{array}{ccc|ccc|ccl} a & b & c & e & c & d & H & & \\ \hline\hline 0 & 0 & 0 & 0 & 0 & 0 & 0 & & \\ 0 & 0 & 0 & 0 & 0 & 1 & 0 & & \\ 0 & 0 & 1 & 1 & 1 & 0 & 0 & & ⬅ \\ 0 & 0 & 1 & 1 & 1 & 1 & 1 & & \\ 0 & 1 & 0 & 0 & 0 & 0 & 0 & & \\ 0 & 1 & 0 & 0 & 0 & 1 & 0 & & \\ 0 & 1 & 1 & 0 & 1 & 0 & 1 & & \\ 0 & 1 & 1 & 0 & 1 & 1 & 1 & & \\ 1 & 0 & 0 & 1 & 0 & 0 & 0 & & \\ 1 & 0 & 0 & 1 & 0 & 1 & 1 & & ⬅ \\ 1 & 0 & 1 & 0 & 1 & 0 & 1 & & \\ 1 & 0 & 1 & 0 & 1 & 1 & 1 & & \\ 1 & 1 & 0 & 0 & 0 & 0 & 0 & & \\ 1 & 1 & 0 & 0 & 0 & 1 & 0 & & \\ 1 & 1 & 1 & 0 & 1 & 0 & 1 & & \\ 1 & 1 & 1 & 0 & 1 & 1 & 1 & & \\ \end{array}$$

Thus, we have tagged the "special" lines with e = 1 and all "regular" lines with e = 0, thus

$$\text{Regular lines:}\quad\quad \overline{e}c \quad\quad \text{Our observation that for most lines $H = c$}$$ $$\text{Line 4:}\quad\quad ecd \quad\quad \text{First tagged group, second line.}$$ $$\text{Line 10:}\quad\quad e\overline{c}d \quad\quad \text{Second tagged group, first line.}$$

Therefore, we can write F as $$ F(e,c,d) = \bar{e}c \vee ecd \vee e\bar{c}d$$ With the truth table for F (right hand side of table) done, we can read G as $$G(a,b,c) = \overline{a} \overline{b}c \vee a\overline{b} \overline{c}$$

Problem solved. I reiterate that I think it's a poor question/problem, because both gates are in fact not "obvious" simple logic gates. Still, I hope you could take away something from my solution to this problem.