Alternating ON/OFF with Logic Gates in a Simulator

I'm going to hand wave over a lot of detail here, but the short answer is that your "b" is correct. You effectively have a race condition and in order to answer exactly what happens you need to know about the propagation delay of your logic (and if we want to really dive into the nitty gritty wire delay etc). You would need to know how the 3 bit counter is implemented (e.g. with which gates and how those gates are implemented) and the propagation delays of the gates. You can think of the propagation delay of the gate as the "delay" of the gate. For example, if you take an inverter and toggle the input there's some delay till the output stabilizes. Take a look at this data sheet and search for "tphl" and "tplh". Notice that the two propagation times are not equal.

It is not necessarily true (in fact it is very probably necessarily not true) that all outputs of the counter toggle at the exact same time. Some outputs (depending on the implementation the more significant bit outputs) will require more logic and thus probably have a greater combinatatorial path to path to output (read more propagation delay). Furthermore there is no reason to assume that the inputs to the counter start at 3'b000. With these two facts the output of the counter will run around like crazy (the shortest combinatorial path way will gate the max output frequency e.g. the shortest combinatorial path will limit how fast the fastest output bit changes). Your display won't be able to keep up with the counter and will effectively display "random" numbers (obviously what the display actually shows depends a lot on its implementation).

For a simplistic, but similar example google "ring oscillator" (but don't build one unless it's for educational purposes only!) and "propagation delay of logic gates".

What you call an ":" is a divide symbol, NOT a ":".

Below Divide = "/". :

So /32 = divide by 32 = 5 stage counter.
Each stage divides by 2 in a binary counter (eg CD4040) so for 1 2 3 4 5 stages the divide ratio is 2 4 8 16 32.

/2 is a one stage counter = a flipflop configured to toggle when clocked.

The bottom lines do what the labels says = reset line.
The dividers are reset to 00000 and 0 respectively.

The box labelled "td" is explained in note 2 - it's a time delay - read the note.It's not complicated - it means EXACTLY what it says. ie there is a delay due to physical circuit parameters.