Wow, I would've expected the 133MHz ATA/IDE interface would be too fast for an ATmega chip, but it looks like they use it in ATA33 (33MHz) mode, somehow getting it to work with a 4MHz(!) ATmega32.
In this case you shouldn't have any problems with a SATA to IDE converter, since they're designed to support older ATA33 devices.
Note however that the OS SCSI stack is only used for SATA devices. IDE uses a different command set, so you won't see SCSI commands arriving at your ATmega, if that's your intention. (The host PC will certainly issue SCSI commands though, and the SATA to IDE device will translate.)
An alternative that might be easier to achieve is to use a USB interface chip to make your ATmega appear as a USB hard drive. AFAIK this does use the SCSI protocol (perhaps a limited subset of it though), so you would see SCSI commands arriving on your device. Recent PCs can boot off a USB hard drive too, if that's your need for connecting directly to SATA.
This solution would be much less sensitive to timing too, as the USB chip would talk over the USB bus at the correct speeds, allowing you to talk to the chip at whatever speed you can manage.
Fig 1 on page 5 of BTM-Datasheet contains numbering of Pins
Are you sure you read '1' on reset input? Since it is stated that the input is debounced it seems to be inteded that it may be connected to some reset button that should be switch to high then pressed to trigger high active reset input.
Also if its pulled up and you need to keep it pulled to ground to not reset that would constantly draw an small amount of current, which you normally want to reduce as much as possible since bluetooth devices mostly are battery powered.
The datasheet itself is not very comprehensive. it does not even contain information about energy consumption or how to access the eeprom
Best Answer
First, I'm going to assume this is what you are looking for:
Comment below if this isn't exactly what you're looking for.
Pretty much all xmega (maybe even all) devices feature IO pins with select-able internal pullup/pulldown resistors.
This is the IO block diagram for an xmega-AU device:
Notice that the top-right section of the general IO pin block diagram has select-able internal pull-up and pull-down functionality, as well as a pull keep or totem pole input options. This is common across all IO pins configurable as general IO pins.
That just leaves hardware SPI functionality. Luckily, the same xmega-AU device supports hardware SPI in both master and slave modes. See chapter 22 for full details on what is supported.
This is not exclusive to the xmega-AU series, this just happened to be the first one I clicked on. IIRC, pretty much all xmega chips have the same or very similar general IO block diagram, and they also support hardware SPI in master and slave modes.