attinyavrdatasheetgpio-external-interruptinterrupts
I faced with some confusion in subject datasheet:
In one section PA.2 should be masking by PCIE1 bit as PA.2 is PCINT2 input and it should be within PCINT[7:0] and PCINT[15:12] range:
On the other hand PA.2 (PCINT2) will generate Pin change interrupt 0:
Is there something that I misunderstood? Or I just faced with a rare case of an error in documentation?
Left goes to mains, middle to your appliance, right goes to ground (maybe via a resistor??). The difference between 5503 and 5508 is that 5503 disconnects both sides of the lamp when off, while 5508 keeps the ground side connected. So the '(un)switched neutral' refers to the neutral of the lamp only.
I don't see the purpose of the 'disconnect the lamp's neutral': the other side of the lamp is still connected to the neutral via the load, so for safety purposes it is still connected.
The mismatch condition will set the interrupt flag, and reading the port removes the mismatch, but doing so does not clear the flag, you must still clear it manually inside the isr.
From port B circuitry shown in the datasheet (Figure 3-4) you can tell that there is no way that WR (asserted during port writes) could remove the mismatch when the pin is configured as an input (TRIS bit is 1), because the WR signal does not affect anything but the "Data Latch", and the output of the data latch doesn't go anywhere because the tri-state buffer is in high impedance when the TRIS bit is 1.
The information missing here is that a port write also triggers port read, because all writes are really read-modify-write operations. The datasheet says this explicitly about port A, but I suspect it works the same way on port B. This means that when you write to the port, a read is actually performed as well, so RD is asserted, removing the mismatch.
However, the mismatch being removed when you write to the port does not affect the fact that the interrupt is called, because the flag is still set, which is the only thing you need to worry about. Your code does not change, you would still perform a read and then clear the flag when you enter the isr.
You may be wondering if a read or a read-modify-write operation occurs at exactly the same time as the input change may make it miss a mismatch condition. It does not, the flag is should still be set. This is because of the input latch controlled by a signal Q1 (which is not mentioned in the text). It basically keeps the input value for the mismatch comparison during the part of the read cycle in which the RD is being asserted, so that the mismatch is still caught.
Best Answer
To be honest, errors in documentation aren't that rare, especially with companies that make tons of large documents.
In this case, my experience is that the register description and Pin-Package drawing are correct. As you should expect. Register interactions are documented during chip design, as is pin-out, whereas those tables are an after-though during or after testing.
I have not had problems with these exact chips going by register descriptions for the PCINTs (never use those tables) and I'm sure I have used PA2 for interrupts several times now, though I have used so many Atmels, it's all a bit of a blur.
EDIT:
Though seeing as the number of pins that are of different PCIE group is also not consistent on further look (2 mentioned in the table, 4 implied in the register description) I do advise a test. You-never-knows strong in this one are.