I'm trying to design an accelerated CPU (65816) for the Apple IIGS by using a high speed ARM processor combined with a software emulator + software emulated cache. The CPU I'm using is the LPC4300 series, which runs at a high speed (200+ MHz) and also has large amounts of internal SRAM which can be used as the emulated cache.
The problem is that the LPC4300 is based on 3.3V logic, while the IIGS motherboard expects 5V. For most of the pins, I can use a standard bus-transceiver to perform the 3.3-5V conversion. Even most bi-directional pins (for example, the data pins on the CPU) can be handled in this fashion, so long as the bus transceiver has 3-state outputs and enable and direction pins. The problem is with the 'RDY' pin on the 65816, which is both bi-directional but does not have any other pin indicating the direction. The function of the 'RDY' pin (as quoted from the datasheet) is as follows:
2.24 Ready (RDY)
The Ready is a bi-directional signal. When it is an output it indicates that a Wait for Interrupt instruction has been
executed halting operation of the microprocessor. A low input logic
level will halt the microprocessor in its current state. Returning RDY
to the active high state releases the microprocessor to continue
processing following the next PHI2 negative transition. The RDY signal
is internally pulled low following the execution of a Wait for
Interrupt instruction, and then returned to the high state when a
RESB, ABORTB, NMIB, or IRQB external interrupt is active. This feature
may be used to reduce interrupt latency by executing the WAI
instruction and waiting for an interrupt to begin processing. If the
IRQB Disable flag has been set, the next instruction will be executed
when the IRQB occurs. The processor will not stop after a WAI
instruction if RDY has been forced to a high state. The STP
instruction has no effect on RDY. The RDY pin has an active pull-up
and when outputting a low level, the pull-up is turned off to reduce
power. The RDY pin can be wired ORed
I do not see a way to use a standard logic level converter here, since it seems that the direction of RDY is not reflected anywhere else. Any suggestions or ideas?
Best Answer
One simple and flexible solution could be mapping the legacy signal to two signals on your module - one a dedicated input, the other a (sometimes) output.
You'll often see something somewhat similar in organization done with FPGA designs, where the internal signals have dedicated direction, and a tri-state buffer is applied to join them to an external bidirectional bus only at the level of the actual I/O pin blocks, controlled by an enable signal generated internally.