You can build the mux with 4 NOR gates, too. It doesn't require extra inverters on the inputs and outputs, if that's what you were doing. Note that the sense of the "select" input is inverted, so you need to swap the "A" and "B" inputs to compensate.
If we allow exor gates then here is a solution.
1st col 4th map: (A exor C) + AB
2nd col 2nd map: (A exor B) + ABC
2nd col 3rd map: !(A exor C) + AB, alternatively (A exnor C) + AB
Edit:
Take col 1 map 4 for example. The first two columns have a pattern I recognize as an XOR gate. First row is 01, second row is 10. Now I look at the boxes with '1', A changes when jumping between the two. Look for another variable that is also changing; in this case it is C. A and C are either 01 or 10 in the '1' boxes: that is the characteristics of an XOR gate. Only two '1' remain in the map and they are grouped into the term AB.
Now col 2 map 2: Here are two groups that will work for an XOR gate; col 1 & 4, and col 3 & 4. The first group produces an XOR gate, the second an XNOR gate. In the XNOR gate, both inputs must be equal to produce a '1' on the output.
Finally col 2 map 3. This map looks like col 1 map 4, except the XOR pattern is reversed. That means we use an XNOR gate instead of the XOR in the first map, or we add an inverter to the XOR output.
By the way, regarding your equation for col 1 map 4, notice that the two bottom corners both have '1'. You can group them to produce the term A!C, reducing your third term to two variables.
Best Answer
1) It shouldn't apply at all to a multiplexer if we're talking about the same thing. A multiplexer is (to me) a device that has many inputs and one output and uses selection pins to tell it which input should be routed to the output.
2) If the two sets of gates implement the same boolean function then it does not matter what gates are used in the implementation of that function. There are multiple correct implementations (but not multiple correct implementations that minimize the number of gates used).