Charge pump output resistance

If you want simple solution, there are lots of ICs named 'high side n-MOS driver' all over the world. Linear Technology, Maxim, Micrel and other manufacturers make them. Just choose what exactly fits your needs.

If you want to konw, how they designed, then... As discrete solution voltage multiplier circuits are commonly used. So you're on right way. Simplest boost circuit i know consists only of capacitor and a diode (shown at left).

^{simulate this circuit – Schematic created using CircuitLab}

This circuit use Vin voltage when load is off to charge capacitor and then use it to boost gate voltage. Drawback is that capacitor will discharge by leakage currents, so ot need to switch off and on load time-to-time.

So in general boost need independent clock source to pump charge (you're on right way here too). One solution is to use Villard cascade voltage multiplier. Schematic shown at right show charge pump circuit providing gate voltage Vin+V(~f) with single cascade. If higher gate voltage required more cascades can be added.

Note, resistor inserted between pump and controlling circuit, so switching off does not cause complete discharge of capacitors. In industry-made gate drivers push-pull cascade is used, providing very fast switching thus reducing switching power dissipation and reduce quiescent current through pump.

ADD: I found tips in industry made gate drivers:

1. One end of pump capacitor is feed from MOSFET source, so it is naturally boosted when transistor is switched on. Thus it acts like my left schematic on this thansition.

2. Another end of pump capacitor is typically fed from LDO. It is need to limit Vgs.

3. There may be no output capacitor (like C3 on y scheme), thus internal MOSFET capacitance to keep gate voltage while pump capacitor is recharged in steady turned-on state.

4. Sometimes there's no pushpull output cascade, pump capacitor is discharged when MOSFET is turned off (like on your schematics). This typical to dirvers not designed for PWM applications.

Charge pumps driven from square waves have inherent apparent series resistance based on the frequency, and the size of the pump capacitor. You expect the output voltage to drop as it is loaded with decreasing resistance.

However, your table shows the opposite. Either you measured something wrong or wrote down the data wrong, or there is something else going on here. Keep in mind that in this case you have a feedback loop that adjusts the PWM duty cycle and possibly the period to keep the 11.9 V output regulated. This may be causing various non-obvious affects on the charge pump output. The pulses are there for another purpose and the charge pump is coming along for the ride.

This probably doesn't matter much if you only want a few mA, like the negative supply of a opamp. Make sure to filter this well before using it to power a opamp. I'd put a ferrite chip inductor followed by a 20 µF or so ceramic cap to ground before the opamp power pin at least, maybe two of those filters in series. The opamp will have some supply rejection capability, but that won't work well at high frequencies. You need to filter out enough of the high frequency noise from the charge pump supply so that the active circuit in the opamp can handle the rest.

Added:

You are now measuring the negative supply voltage with a fixed 1 kΩ load on it, while varying the load on the positive supply. The relationship you measured makes sense. By increasing the load on the positive supply, the feedback mechanism increases the duty cycle and/or frequency of the switching pulses. This lowers the effective resitance of the charge pump negative supply. This is all a consequence of the pulses being produced for the purpose of regulating the positive supply, which is not necessarily optimal for regulating the negative supply. The harder the switcher has to work to maintain the positive supply, the better job it does of driving the negative supply too.