integrated-circuitsimulation
Simulating the circuit below (PMOS charge pump; doubles the input supply), all the transistors are operating in cutoff region when I extracted the .dp0 file. What might this means? I'm using SYNOPSYS in simulating. 
Is there might be a problem here or what could be the problem if it's in cutoff? Because I've read some papers about it and it should be linearized (triode region) which I've tried to but it wont. What factors might be affecting the operation?
Yes, you are correct in your last example, assuming a red LED with 2.0V over it, the current will be \$\frac{(10-2)V}{470Ω} \approx 17mA\$. For your first example, I assume you already know that the total resistance of something in parallel is \$\frac{1}{R} = \frac{1}{R_1} + \frac{1}{R_2} + \dots + \frac{1}{R_n}\$ and you are struggling of how to calculate the total resistance of 100Ω, 200Ω and the LED, right? I am not sure if it is possible to do it that way. Instead look at each of the current paths. Some current will flow through \$R_1\$ (470Ω) and further through \$R_2\$ (200Ω). Let's call this current \$I_A\$. Then some current will flow through \$R_1\$, through \$R_3\$ and the LED, \$I_B\$.
Let's call the voltages over \$R_1\$, \$R_2\$ and \$R_3\$ for \$U_1\$, \$U_2\$ and \$U_3\$. Then \$U_1 = (I_A + I_B) \times R_1\$, \$U_2 = I_A \times R_2\$ and \$U_3 = I_B \times R_3\$. The voltage over \$R_2\$ will be the same as over \$R_3\$ and the LED combined, i.e. \$U_2 = U_3 + U_{LED}\$. You already know that the total voltage over all components is 10V. So
\$U_1 + U_2 = 10V\$
\$U_1 + U_3 + U_{LED} = 10V\$
and this gives you two equations with two unknowns, \$I_A\$ and \$I_B\$, which is standard math to solve.
To answer my own question: it seems LTspice requires text files to be saved with Windows Latin 1 code page, CRLF line endings. I'm using Wine on a Mac, and my text-editor saves as UTF-8 by default. I'm guessing LTspice misinterprets the UTF-8 µ on capacitor values as something invalid, but confusingly doesn't throw an error message.
Best Answer
Maybe I'm missing something because I don't know SYNOPSYS, but it looks to me as if there is no DC path through the circuit. Isn't C54 blocking any DC from reaching ground?
Also none of the PMOS devices have anything but leakage current to define the gate potential when their driver transistors are in the OFF state.
The PMOS symbols look strange : surely the transistor substrate should be at source potential, not connected to drain?