CMOS gate logic switching time based on input vectors


My question is regarding CMOS logic gates switching time based on input.

Say I have a NAND gate and my input vectors are:

00 | 1
01 | 1
11 | 0
10 | 1

So, the output is not switching in case of the first 2 vectors and switches for the rest.

I would like to know if the gate will temporarily lose its Logic 1 state and in the process adding to compute time when the input toggles from:

00 ---> 01

I need to know this as I have built a gate level netlist (verilog) simulator which adds to compute time only when the output toggles. I need to know if my approach should look at the input values instead.

Best Answer

@sanjay: A standard CMOS NAND gate has two PMOS devices in parallel to pull the output (to supply) and two series NAND gates to pull the output down (to ground). If either input is zero, then at least one PMOS is on pulling the output up and at least one of the series NMOS FETs is off preventing the output from pulling down.

So the output will not "lose its state." There can be small glitches seen in the output voltage when the one input changes from 0 to 1 due to gate overlap capacitance in the FETs, but any glitches like this should be small enough that they do not cause the next gate or stage to see a change in the NAND output.

Note we don't usually consider a combinational logic gate as having a "state." In digital design, a "state" implies some sort of memory or latched condition as in a flip-flop or latch.

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