Common-Mode Voltage

TMDS is actually a current mode standard, so the current flowing (or not flowing) in each line represents the bit level. It is therefore not necessary to drive the line both high and low, only to pull it in one direction on the transmit side. The bus ends up having a voltage swing of significantly less than 1 volt, making it less likely to generate or receive interference.

Now, in this case there is a DC return path through the shield. This doesn't work with a voltage mode standard as the current will be time-varying. Just look at how the transmitter is configured - a constant current source that is switched over to one side of the pair or the other. The current through the source is constant, and it is always connected to the shield, so that current will be DC. The idea is to avoid a high frequency return path through ground.

On this circuit, I believe you can do a common-mode/differential analysis that assumes the switch is in each position for 1/2 of the time and get what appears to be a differential return current in the opposing pair.

My question is, why should we try to impedance match a differential pair connecting CML devices? Does differential impedance even mean anything since the conductors will never carry equal and opposite signals?

You have to dislocate the DC scenario from the superimposed AC signalling. Numerically the current may not reverse but, as far as sending data down a balanced pair of wires you need a balanced load.

Would it not be better to treat each conductor individually and match them to the single ended impedance of the devices?

However, twisted pair is a tad notorious because it tends to require a balanced load that is not only transverse but longitudanal as well so, your 2nd quote does carry a certain amount of decent weight of truth.

In my experience with +100Mbps data signalling I've tended to fall towards treating a piece of twisted pair as two individual wires and used 2 balanced load impedances connected to screen.