Constant Bit Signal in VHDL

fpgavhdl

I need to declare a bit with the constant value of 1.

What almost worked was:

signal name: bit := '1';

but the value of "name" is always '0' in this case.

How can I do this properly?

Full code:

ENTITY sleA IS
PORT(
    signal sel: std_logic; 
    A: in bit_vector (3 downto 0);
    S: out bit_vector (3 downto 0)
);
end sleA;
architecture arq_sleA of sleA is
begin
    sel <= '1';
    S(3) <= ((not sel) and A(3)) or (sel and A(2));
    S(2) <= ((not sel) and A(2)) or (sel and A(1));
    S(1) <= ((not sel) and A(1)) or (sel and A(0));
    S(0) <= ((not sel) and A(0)) or (sel and sel);
end arq_sleA;

Best Answer

If sel is an input for the entity then you can set the initial value in the entity's port:

port(
  sel: in std_logic := '1';
  A: in bit_vector (3 downto 0);
  S: out bit_vector (3 downto 0)
);

This will work in simulation, but for synthesis make sure your target technology supports initial "power-on" values (true for FPGAs, not so for ASICs). See Is initialization necessary?

Also note that signal is only used in the architecture body, not entity declaration.

Related Solutions

Electronic – Problem getting VHDL syntax correct

VHDL accepts the ISO 8859-1 character set, this is UTF-8.

Your VHDL analyzer is having problems with some of the characters as a result of you copying the text directly from a book.

Your comments aren't delineated by two dashes (e.g. --), your double quotation marks all need to be replaced with ".

After which the VHDL code analyzes.

There's no discernible reason why d3, d2, d1, and d0 can't be replaced with a bit_vector. There may uses with the present port interface in the book.

Formal ports are associated with actual signals in an association list. It's possible to associate individual elements of a vector with a base element.

Converting between non-closely related types can be done with conversion routines:

-- bcd_7seg.vhd
-- bcd-to-seven-segment decoder
entity bcd_7seg is
    port(
    d3, d2, d1, d0: in bit;
    a, b, c, d, e, f, g: out bit
    );
end entity;
architecture seven_segment of bcd_7seg is
    signal input : bit_vector (3 downto 0);
    signal output: bit_vector (6 downto 0);
begin
    input <= d3 & d2 & d1 & d0;
    with input select
        output <= "0000001" when "0000",
                  "1001111" when "0001",
                  "0010010" when "0010",
                  "0000110" when "0011",
                  "1001100" when "0100",
                  "0100100" when "0101",
                  "1100000" when "0110",
                  "0001111" when "0111",
                  "0000000" when "1000",
                  "0001100" when "1001",
                  "1111111" when others;
-- separate the output vector to make individual pin outputs.
    a <= output(6);
    b <= output(5);
    c <= output(4);
    d <= output(3);
    e <= output(2);
    f <= output(1);
    g <= output(0);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity bcd_tb is
end entity;

architecture foo of bcd_tb is
    signal d:  std_logic_vector (3 downto 0) := "0100";
    signal output:    std_logic_vector (6 downto 0);
begin
DUT:
    entity work.bcd_7seg
        port map (
            d3 => to_bit(d(3)),
            d2 => to_bit(d(2)),
            d1 => to_bit(d(1)),
            d0 => to_bit(d(0)),
            to_stdulogic(a) => output(6),
            to_stdulogic(b) => output(5),
            to_stdulogic(c) => output(4),
            to_stdulogic(d) => output(3),
            to_stdulogic(e) => output(2),
            to_stdulogic(f) => output(1),
            to_stdulogic(g) => output(0)
        );
end architecture;

You can also associate individual elements of an array type port with the base element type or use conversion functions as are shown above for converting between type bit and the element type for std_logic_vector.

VHDL – Resolving Illegal Reference of a Signal During Static Elaboration

It's helpful when asking VHDL to question to provide a minimal, complete, and verifiable example pointing to an error.

Here's a solution:

library ieee;
use ieee.std_logic_1164.all;

entity some_entity is
    generic (n: natural := 9);
    port (
        x:    in  std_logic_vector (n-1 downto 0)
    );  
end entity;

architecture foo of some_entity is
begin
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity some_entity_tb is
end entity;

architecture foo of some_entity_tb is
    constant n: natural := 9;
    signal signal_id:   std_logic_vector (n - 2 downto 0);
begin
INSTANTIATED:
    entity work.some_entity
        generic map (n)
        port map (
            x(n-2 downto 0) => signal_id,
            x(n-1) => '0'
        );
end architecture;

The entire bit analyzes and some_entity_tb elaborates and runs (without actually doing anything useful other than proving connectivity).

You have the ability in VHDL (incl. -93) to associate elements (members) of an array port formal separately.

IEEE Std 1076-1993 4.3.2.2 Association lists, para 14:

A formal may be either an explicitly declared interface object or member (see Section 3) of such an interface object. In the former case,such a formal is said to be associated in whole. In the latter cases,named association must be used to associate the formal and actual; the subelements of such a formal are said to be associated individually. Furthermore, every scalar subelement of the explicitly declared interface object must be associated exactly once with an actual (or subelement thereof)in the same association list, and all such associations must appear in a contiguous sequence within that association list. Each association element that associates a slice or subelement (or slice thereof) of an interface object must identify the formal with a locally static name.

And to explain where the error message:

ncvhdl_p: *E,ILSGRD (test.vhd,159|32): illegal reference of a signal (SIGNAL_ID) during static elaboration [12.3].

came from:

IEEE Std 1076-1993, 12.3 Elaboration of a declarative part, para 3:

In certain cases, the elaboration of a declarative item involves the evaluation of expressions that appear within the declarative item. The value of any object denoted by a primary in such an expression must be defined at the time the primary is read (see 4.3.2 ). In addition, if a primary in such an expression is a function call, then the value of any object denoted by or appearing as a part of an actual designator in the function call must be defined at the time the expression is evaluated.

It's telling you that you can't assign an expression as an actual to a formal unless the value of the object signal_id is known at elaboration time, and a signal's value isn't known until after elaboration:

NOTE--It is a consequence of this rule that the name of a signal declared within a block cannot be referenced in expressions appearing in declarative items within that block, an inner block, or process statement; nor can it be passed as a parameter to a function called during the elaboration of the block. These restrictions exist because the value of a signal is not defined until after the design hierarchy is elaborated. However, a signal parameter name maybe used within expressions in declarative items within a subprogram declarative part, provided that the subprogram is only called after simulation begins,because the value of every signal will be defined by that time.

Best Answer

Related Solutions

Electronic – Problem getting VHDL syntax correct

VHDL – Resolving Illegal Reference of a Signal During Static Elaboration

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