Counter in Verilog

fpga

I am a beginner in verilog and I am trying to write a counter program. My aim is to increment the count value whenever I press the switch Sw. Following is my program. But I am getting some syntax error at the second if. I am unable to unerstand it. Please help.

Thanks in advance.

module counter (clk,reset,led,sw);
input clk,reset,sw;
output [3:0] led;
reg [3:0] count; 
integer temp = 0;
always @ (*)
    if (~reset)
        count <= 4'b0;
    else if (~sw & posedge clk)
        temp =1;
    else
        count <= count;
    if (temp==1)
        begin
            count <= count +1;
            temp =0;
        end
    else
        count <= count;
assign led = count [3:0];       
    endmodule

Best Answer

The second 'if' statement is not part of the 'always' block. Try putting 'begin' and 'end' around the logic you want to group.

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