PCB Creepage – Managing Creepage Between Layers

I would recommend the IPC: IPC2221A. They are conservative BUT most testhouses that then underwrite your design will only do so against the IPC. The IPC2221A become very annoying for uncoated terminals, especially at elevation. Personally I have been using the British Standards for uncoated clearance (for elevation & pollution) with an additional factor on top.

For voltages greater than 500V, the (per volt) table values must be added to the 500V values. For example, the electrical spacing for a Type B1 board with 600V is calculated as: 600V - 500V = 100V 0.25 mm + (100V x 0.0025 mm) = 0.50 mm clearance

One thing to be clear though is when you say 500V do you mean?

• Working voltage

• Peak working voltage

• Transient voltage

• Repetitive transient voltage

Dirac pulse voltage

• Repetitive Dirac pulse voltage (eg switching spikes)

The ones marked with * are the ones you should be using to determining the voltage to derives clearance. The only one that isn't Dirac pulse voltage that isn't repetitive (you will have to define what you class as repetitive) & if you see some high spikes then the dielectric breakdown of the FR3/Prepreg will have to be used.

On the topic of prepreg, I would advise the use of double prepreg IF it is to be used to separate high potentials. Even though prepreg at the standard thickness used should in theory provide 4kV of voltage withstand, there have been some annoying instance of poor quality prepreg or poor handled prepreg causing breakdown.

NOTE it really should be creepage, not clearance.

Creepage is the separation between two conductors as measured along the surface/layers of a board.

Clearance denotes the shortest distance between two conductive parts as measured through the air.

You does not need to drive the LEDs via an isolator.

First of all, Ethernet specifies 1.5 kVrms @ 50/60 Hz @ 1 min basic isolation. What does it mean? It means that typically the voltage applied/existing between the sides of the isolating transformer must be around zero all the time the device works and only during the specified time (generally, once in the life cycle) the voltage could be 1500 Vrms sine (not distorted heavily) continuously during 60 sec max. Once you'll have that voltage happen you need to stop using the device and re-test its isolation properties. It is hard to say before what voltage difference between the transformer sides (windings) the device will still work, but the basic isolation conditions mean that any voltage outside a "technical" zero leads the device not to work. For opposite example to an Ethernet transformer for which only basic isolation parameters (Viso @ freq @ time) are specified, an ADuM isolating device is additionally determined with the parameters (Viorm < Viso) specifying the max voltage diff between the chip sides before which the device will continue its function properly.

Second, look at your design. Why do you aware about the tx/rx pairs but not about the traces from RJ45 to the BS termination? And why not between the LEDs traces and the chassis ground? Also, recall that the RJ45 jack has a metal shield connected to (chassis?) ground and the only one that separates it from the tx/rx pairs is the top mask layer. Again, wired Ethernet is designed to (properly) operate in well-grounded, earthed environments where a hi-pot between a two points shall not occur. If a hi-pot occurs it is a fault condition and the points must (try to) withstand it during a very short time a little bit (but guaranteed) longer that the time needed by an external devices (breakers) to isolate/eliminate/shutdown/etc the hi-pot and/or fault conditions. If you need to deal with hi-pot and/or other electrical faults, you need to use glass/plastic fiber optic Ethernet.

Third and last, there are many pcb routing examples provided by Ethernet chip manufacturers, i think there are may cases similar to your interest/design goals. You need to lurk more and better :-)