I'm new to EMIF (external memory interfaces) and I ran into kind of a dumb question about DDR3- not super important but mostly me just wondering if there's an answer I'm not thinking of. Basically I'm wondering- if you need to send 12 bits for both the row and column addresses, why is there only one 12 bit address bus?
Is it because the row address needs to arrive first (side question, does it need to arrive first or is that just convention)?
Or is it a due to physical constraints of the number of pins?
Any help or documentation or references would be really appreciated.
Thanks!
Best Answer
Generically speaking, DRAM — whether asynchronous or synchronous, SDR or DDR — receives the row addresses and column addresses multiplexed on a single set of pins.
With older asynchronous DRAM, this is controlled explicitly by the RAS (row address strobe) and CAS (column address strobe) control pins.
With synchronous DRAM of any type, the RAS, CAS and WE pins have been combined into a more generic command bus, but the basic concept is still the same: row addresses and column addresses are transferred on two separate clock cycles.