Delete or ignore I/O from a schematic block in Lattice

I am programming with a Lattice ispMACH 4000ZE Pico DevKit and with the software ispLEVER Classic Project Navigator. I want to use in my schematic file the OSCTIMER block from the Lattice library, but the problem is, that I MUST use all inputs and output, even though I only need one output and one input. How can I ignore the other pins? If I cannot ignore them, how can I delete them? I tried by editing the symbol (I deleted the input and output pins I did not need) but it did not work.

I compile it without problems but when I open the Contraint Editor, this error appears:

Fatal Error 3501: Instance name I26/N_8 cannot be resolvedDone: failed with exit code: 0002.

Thanks again.

EDIT: Oct. 10
So I programmed the clock with VHDL like the documentation showed me:
Advance Features

--Libraries 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

library lattice;
use lattice.components.all;

library MACH;
use MACH.components.all;

entity Int_Clock is

port( 
    CLOCK_OUT : out std_logic);
end;

architecture structural of Int_Clock is

component osctimer
generic(TIMER_DIV : string);

port(   DYNOSCDIS : in std_logic; -- Disable internal oscillator
        TIMERRES : in std_logic;  -- Reset timer
        OSCOUT : out std_logic;   -- Oscillator output
        TIMEROUT : out std_logic); -- Timer output
end component;

signal tmr_out, osc_dis, tmr_rst, osc_out : std_logic; 

begin

I1: OSCTIMER
generic map (TIMER_DIV => "128")

port map (  DYNOSCDIS => osc_dis,
        TIMERRES => tmr_rst,
        OSCOUT => osc_out,
        TIMEROUT => tmr_out);

CLOCK_OUT <= tmr_out; 

end structural;

Again, it compiled without any problems BUT when I wanted to make my JEDEC-File an error appeared:

lpffll.exe stopped working

What does this even mean?! ispLever did not stop working, it actually made my JEDEC-File (I think) but my clock still does not work (I am monitoring it with a oscilloscope).