I'm trying to design and build a simple ac/dc smps that outputs 5v dc and capable of 2 amps. I currently have it mostly designed using a nmos but the problem I'm running into now is how to get a pwm signal with 18V. Is there any advantage to using a PMOS or a NMOS or vice versa? I need to build this soon to stay on track for my project so any input is helpful! I was thinking of using a microcontroller to do the feedback but I understand that I will need a gate driver for it also. I'm not the strongest at programming so I am interested in seeing if there's any ic's or circuitry that I can design that will do the feedback for the pwm input for the gate of the mosfet. I imagine I would still need a gate driver for that option too. I appreciate the help.
Design/Build SMPS- PMOS or NMOS
buckmosfetmosfet-driverpower supplyswitch-mode-power-supply
Related Solutions
Yellow is the critical current flow out, not sure where it goes from the output cap, C3.
Pink is the ground return, kinda sorta, theres a few critical loops in a circuit like this, some follow the path of least resistance, some follow the path of least impedance (follow their supply trace).
Keep in mind your goal is to minimize the size of this loop and minimize the resistance between yellow/pink at high frequency, (minimize impedance to ground).
Lets just quote the datasheet since it covers all of this:
"When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The most impor- tant consideration when completing the layout is the close coupling of the GND connections of the CIN capacitor and the catch diode D1. These ground ends should be close to one another and be connected to the GND plane with at least two through-holes. Place these components as close to the IC as possible. "
C1 and D2 in this case. C1 has a really, really, long path to ground for a power supply decoupling cap. Its also on the other side of the circuit from D2's ground. When your talking about high frequency PCB design when it says "tightly coupled" that doesn't mean just both tied to a ground plane. It means both ground pins are right next to each other, with a surface polygon pour connecting them and multiple via's to a ground plane right next to the pads.
Incidentally aren't your diode silkscreen's backwards?
"Next in importance is the location of the GND con- nection of the COUT capacitor, which should be near the GND connections of CIN and D1."
C3 is the output cap and its ground is roughly as far away from the other 2 as you can get.
"The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with the GND of R2 placed as close as possible to the GND of the IC. The VOUT trace to R1 should be routed away from the inductor and any other traces that are switching."
Think your ok with this one, your probably better off running the trace from C3 further away from the inductor but its probably ok.
"High AC currents flow through the VIN, SW and VOUT traces, so they should be as short and wide as possible. However, making the traces wide increases radiated noise, so the de- signer must make this trade-off. Radiated noise can be de- creased by choosing a shielded inductor."
If were you i'd just use polygon pours for most of these connections, just make sure you have appropriate filtering in place and a shielded inductor.
"The remaining components should also be placed as close as possible to the IC. Please see Application Note AN-1229 for further considerations and the LM2734 demo board as an example of a four-layer layout."
If using 4 layer why not reference that app note? pretty much covers using a big ol' ground pour for the critical ground return and a pour for the SW output.
How about a 2 minute design review?
- Make sure the primary size of the transformer is properly fused. Also include a common mode choke and L-N filter cap for conducted emission suppression. You can get that all in a single package, and I would recommend that for this project.
- 0.012F is a big cap. Some inrush current limiting may be necessary.
- At 400kHz, you will need a gate driver. Usually it is powered from the rectifier side of the switch. You don't show what your turns ratio is on the transformer, but make sure the gate driver's absolute maximum voltage rating isn't exceeded. The gate driver should be able to accept 5V TTL input from your microcontroller.
- Your microcontroller will need powered from the same node as the gate driver. Assuming is a lower power relative to your load, a linear regulator should be fine for that.
- As FakeMoustache said, you want a P channel MOSFET there. There are dedicated gate drivers for driving a P MOSFET in that configuration. Further, you may want to consider synchronous rectification.
- If you're putting this on a PCB, which you should, layout will be critical.
Best Answer
PMOS are more expensive to produce, they have grater Rdson than a copmlementary NMOS, therefore almost all SMPS are using NMOS, because of less generated heat, less size, less price. I don't know if there is a single pros for the PMOS.