Get a PCI style FPGA board that you can use generic IOs for the target 68000 connection. Implement your control system in the FPGA, and write software to tell it what to do. That's basically making your own ICE kit. If the commercial ICE kits are horrendously expensive (check and find out if they are, I don't know), then this could potentially come in cheaper, and give you control over how it works. Check out Raggedstone, Broaddown or Mini-Can FPGA boards, they are relatively inexpensive boards, but not sure if it has enough accessible IO pins for what you need. Then check OpenCores for open-sourced PCI blocks and other things that may be useful. You may also need to add some level shifting stuff on a small PCB addon to these boards. Look up Xilinx/Altera white papers on using Quickswitches between 3.3V FPGA and 5V PCI, hooking the other connections to a 5V 68000 socket would be essentially the same process.
As I remember, the DIP 68000 is 68 pins, and some of those are not used in some systems, such as Amiga does not recommend using some of the 6800 style peripheral pins, and they become disconnected in later Amiga systems.
You don't show what the optos are connected to, but some logic devices (not 74LSxx devices) include "bus-keeper" circuits which behave as weak pull-ups when an input is high, and weak pull-downs when it is low. Such circuitry is often useful, but may cause difficulties when interfacing with logic which doesn't drive very strongly. Still, I would expect that a 10K pull-up should win against a bus keeper.
If the signals from the optos are connected to microcontroller I/O pins, I would suggest that between rows you release all the L1, L2, etc. wires, set the pins to outputs driven "high", then set the pins back to inputs and then drive the proper Lx pin. That approach should let you scan much faster than would otherwise be possible, whether there are bus-keeper circuits or not.
To clarify my later point, pins which are high tend to stay high, and vice versa (due to parasitic capacitance if not bus keepers). The time required for a pin to switch depends how hard it's driven. I would expect that an opto which is "on" would drive a pin low relatively strongly, while a 10K pull-up drives comparatively weakly. If one can disable the optos (e.g. by releasing all the Lx pins high) and use something to unconditionally strongly drive the column pins high (e.g. an I/O port configured as output), it will take almost no time to switch those pins high. If that high drive is then disabled and one Lx pin is driven low, it should be able to quickly switch the appropriate port pin. By contrast, if one simply changed which Lx pin was enabled without precharging the column, it might many many microseconds for the resistor to switch the pin high.
Since you don't have the columns connected to microcontroller I/O pins, you probably don't have a means of pre-charging them. If the only things that can pull the columns high are resistors, the speed at which the columns pull high will be controlled by the resistance. The lower the resistance, the faster the action, but if the resistors are too low the optos won't be able to sink enough current to yield a clean "low". If you want faster action, you could use diodes to connect a port pin to the bus pins such that when the pin is high it pulls all the bus pins high via the diodes.
Best Answer
B19 on the PC104 does no such thing. It is RFSH*, and is used as part of a refresh cycle for dynamic RAM. You need a decoder for A4 - A7 to do what you want.
A 373 will do exactly the opposite of what you want, since it accepts data when LEN is high, and 138 outputs are active low. Use 374s instead.
EDIT - And, of course, I forgot that the ISA bus uses 10-bit IO addressing, which was then carried over to PC104, so a decoder (not needed as long as you stick with this board) will need to operate on A4 - A9.