I am having a hard time understanding difference between parallel adder and serial adder when adding two binary numbers. Wikipedia does not have any information, and google image search is bringing me almost nothing. Can anyone help me here?
Difference between parallel adder and serial adder when adding two binary numbers
digital-logic
Related Solutions
Implement your debounce like this to fully eliminate the effect of the switch contact clatter.
Captured courtesy of this site.
Update
After discussion in the comments section I am adding the below picture to help visualize the "NAND latch" in the DeMorgan equivalent of its logic to show how the latch really is a low true input latch.
No, you can not translate a (nontrivial) circuit that has memory to a combinatorial (feedback-less) circuit.
The outputs of a combinatorial circuit are by definition a function of its inputs (and nothing else).
Take the simplest non-combinatorial circuit: the Set-Rest memory cell (two cross-couples NANDS or NORS). When the inputs have the 'remember' value the outputs are a function of the past. This is simply not possible with any combinatorial circuit.
Best Answer
If you want to add two N-bit numbers, a parallel adder will use N copies of a full-adder circuit, and it will produce a result in one clock cycle.
On the other hand, a serial adder will use just one full-adder circuit, but it will require N clocks to produce the result.
The tradeoff is circuit complexity (and power consumption) vs. time.
Some examples: A desktop PC uses a parallel adder, because it wants to be able to do as much arithmetic as possible in a given amount of time, and there is no real restriction on how much power it can consume. On the other hand, a handheld calculator only needs to be as fast as the human operating it, but it needs to last a long time on a small battery, so it uses a serial adder.