Difference between setting up clocks on Verilog

clocktestverilog

These two statements are used quite often, to set up clocks in test benches:

initial
begin
  clock = 1'b0;
  forever #5 clock = ~clock;
end

always
begin
  clock = 1'b0;
  #5 clock = 1'b1;
  #5;
end

Is there any difference between the two or are they 100% equal and interchangeable?

Best Answer

Your examples are basically the same. However, I only use the first example, with a define for the cycle count. Here's a snippet from my code:

`define CYCLE 100 // in nanoseconds
....

// create a clock depending on the CYCLE setting
initial begin
   clk = 1'b0;
   // every half-CYCLE invert
   forever #(CYCLE/2) clk = ~clk;
end

I prefer to use an initial block for my testbench clock because initial blocks are never synthesized. So putting it inside an initial block makes is quite clear that this code is only for simulation.

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