I have a system that boots at one frequency and then the main PLL is reloaded to continue boot at a higher frequency. When this is done, the DDR is put in to self refresh. After the main PLL locks, the DDR clock will change from 100Mhz to 133Mhz.
It seem that the DLL inside the DDR is related to the clock frequency. Should I re-run the MRS sequences to lock again before operating at the higher frequency?
Bonus: What exactly is the function of the DLL with-in the DDR? I thought everything was run off of CK/CK#. I know the host DDR controller needs some delays for latching data, but I thought DDR was designed so the RAM could be simpler.
The specific DDR2 I am using is Micron MT47H32M16 and Samsung K4T51163QG-HC.
Best Answer
The datasheet for the RAM chips covers changing clock frequencies. For example, the Micron DDR2 datasheet says on page 40:
There are sections in the datasheet that cover each of these situations, with timing diagrams. You should read them to understand exactly what conditions you need to meet.
Note also that the minimum frequency spec for DDR2 is 125 MHz. It may work at 100 MHz but it is out of spec and therefore not guaranteed.
As for why DLLs, according to this article it keeps the RAM simple but moves complexity into the controller. (The author's company sells memory controller IP though so they may be biased.) Since output data is aligned to CK, a DLL is needed to manage the CK to DQ output delay.