I'm trying to implement an SPI device in Verilog. I'm having a lot of problems for coordinating master and slave, since sometimes (with my current impl.) the SPI master device doesn't send enough clock pulses to the slave so it can finish its processing.
For instance, this can occur if the slave is implemented so that its state machine has more states, and it stops receiving clock pulses before it finishes completing its cycle.
I could modify my implementation to make these two devices to be coordinated in terms of clock pulses, however, this means that the master implementer needs to know the impl. details of the slave (and all the potential slaves). This doesn't seem right to me at all.
Does the SPI protocol specify exactly how many pulses the master must provide to the slave when sending, for instance, one byte? If not, how is that any SPI master device is compatible with any slave? Would it be ok to send a ton of pulses (e.g.: 64 pulses for 1 byte) to the slave just in case?
Best Answer
The SPI master is not responsible for making sure that the slave's internal state machine gets 'enough' clock pulses. All the master is responsible for is one clock pulse per bit transferred to or from the slave - that's it.
If your slave needs additional clocking then it's up to you to manage your implementation in a way which supports this - maybe you specify some minimum number of bytes must be transferred (even if some of them are 'dummy' bytes), or maybe you have to provide an external clock to the slave in addition to the SPI clock.
A well-behaved SPI slave should reset its SPI state machine when its slave-select input is deactivated so that whatever the master does in one round of comms doesn't necessarily break the next round due to something being in an incomplete state.