EEPROM address definitions and delay

eeprompic

I am using 24LC256 EEPROM which have addresses from 0x0000-0x7fff. But I would like to predefine certain address from EEPROM to specific tasks, like from 0-100 for task-1 and so on.

Does predefining those addresses in the C code work?

Like:

const int add[31] =   {0,4,8,12,16,20,24,28,32,36,40};

Will it work or should we point address as 0x0000 - 0x7fff?

And my other question is, how much delay must be done after writing operation (simple write/Page write) in an EEPROM.

Best Answer

The first is a programming issue and the rest of your code will decide how you want to designate the sections of the device.

For the second, the datasheet gives a maximum of 5ms to program a byte or page, but you can use acknowledge polling to check if the device has completed the operation before that time has elapsed; see section 7.0, "Acknowledge Polling" of the Microchip 24AA256/24LC256/24FC256 datasheet for details.

Related Solutions

Electronic – EEPROM data check

The problem with your approach is that the EEPROM data is permanent, whereas the variable is volatile. Once the device is power cycled, how will you check the data in the future? The variable is gone, and all you have is the EEPROM copy.

What you have so far is not a data integrity strategy, but only a write verification step (which is wortwhile; don't misunderstand).

You could store checksums along with the data; however, checksums can only tell you that the data is corrupted. This is better than proceeding with corrupted data; however, if the data is critical, it means that the device has failed.

A more robust solution is to store the data in such a way that not only error detection is possible, but also error correction.

You can implement a Hamming codes for individual words of the data. A Hamming code can recover from a single-bit error; more with some extensions.

If you have lots of space on the EEPROM, you can implement redundancy. For instance, you can split the EEPROM into two halves which mirror each other, similar to a RAID0 scheme used for hard disks. Write every unit of data in both partitions, with block checksums. When reading data, if a checksum is bad, you can try the other copy it in the mirrored partition. Chances are its checksum is good. (And if so, you can overwrite the bad copy with the good copy to repair it.)

Electronic – CRC for eeprom data check

While the suggested approach from PeterJ is fine, its cleaner to decouple the "data layer" logic (EEPROM access) from the CRC routine.

This CRC-32 can be universally used, its not bound to program specific behavior:

// CCITT CRC-32 (Autodin II) polynomial
uint32_t CalcCRC32(uint32_t crc, uint8_t *buffer, uint16_t length) {
    while(length--) {
        crc = crc ^ *buffer++; 

        for (uint8_t j=0; j < 8; j++) { 
           if (crc & 1) 
              crc = (crc >> 1) ^ 0xEDB88320; 
           else 
              crc = crc >> 1; 
        } 
    } 

   return crc; 
}

Then you just feed blocks of data to the CRC function like you see fit and as required by your application.

This usage example is just written down. It uses the fictional function eeprom_read() which reads a block of data from EEPROM. We start at EEPROM address 0.

const uint8_t BLOCKLENGTH = 128;
uint32_t crc32;
uint8_t buffer[BLOCKLENGTH];    // temporary data buffer

crc32 = 0xFFFFFFFF;  // initial CRC value 

for (uint16_t i=0; i < NUMBEROFBLOCKS; i++) {
    eeprom_read(BLOCKLENGTH * i, buffer, BLOCKLENGTH);    // read block number i from EEPROM into buffer
    crc32 = CalcCRC32(crc32, buffer, BLOCKLENGTH);        // update CRC
}

// crc32 is your final CRC here

Note that NUMBEROFBLOCKS is just a placeholder. I hope you get the idea.

Best Answer

Related Solutions

Electronic – EEPROM data check

Electronic – CRC for eeprom data check

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