Electrical – 3-input XOR gate truth table

You've already derived the equation for the input to the D input of the flip-flop:

D = (J • \$\mathsf{\small \overline{\text{Q}}} \$) + (\$\mathsf{\small \overline{\text{K}}} \$ • Q)

So you can construct a truth table for this equation:

J  K  Q     D
-------    ---

0  0  0     0
0  0  1     1
0  1  0     0
0  1  1     0
1  0  0     1
1  0  1     1
1  1  0     1
1  1  1     0

Note because it is a clocked flip-flop, the Q and \$\mathsf{\small \overline{\text{Q}}} \$ will not reflect the state of D until after the clock pulse (rising edge of Clk).

Also note that when J and K are both 1, the output toggles, which is the correct behavior for a J-K flip-flop.

To answer your actual question, no, the output of a gate is never "Z", unless it's specifically designed as a tristate gate with an output enable.

In general, inputs to gates that are "Z" are treated the same as "X", and the output is either "0", "1" or "X" as appropriate.

For the specific case of the XOR with its inputs tied together, your original statement that input "X" gives output "0" is correct — although many simple-minded logic simulators get this wrong. The problem is that they can't distinguish between two inputs being the same unknown value versus two independent unknown values.